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tps650941 design issue.

Liu Dong
Prodigy 190 points
Other Parts Discussed in Thread: CSD87588N

Dear TI Colleague,

I have a customer use TPS650941 PMIC for intel Apollo lake platform development, now customer has some issue as below :

1. customer want to know the product status and release time ?

2. customer want to know whether TPS65094x support APL memory group status ?(include DDR3L/LPDDR3/LPDDR4).

3. whether TPS65094x finished software firmware , no need OTP Writer ,before customer get the product ?

 

4. Does ti support the reference design or detail Datasheet ? when and how customer get the samples ?

 

5. TPS65094x ‘ Iccmax reached 21A , whether the spec achieved APL spec request ?

 

6. From the datasheet of TPS65094x , Vin =5.4V to 21V , Does Buck1 & Buck2 support VSYS run 4.75 to 5.25V ? if OK , what customer need notice when they design ?

 

7. Can ti support more detail datasheet ? if OK pls send to email : dong.liu@avnet.com


  • 0
    TI__Genius 17380 points

    Hi Liu,

    1. TPS650941 released to market in early September. Due to NDA requirements, the webpage has remained on PREVIEW status as we are unable to release full datasheet without NDA. [Edit: this is no longer the case. Datasheet is available on the web].

    2. Yes, the TPS65094x can support DDR3L/LPDDR3/LPDDR4. The VDDQ rail for the TPS650941 has default voltage of 1.2V for LPDDR3, however this can be changed by I2C up to 1.35V for DDR3L or down to 1.1V for LPDDR4. Depending on demand, we may also make available different version of the TPS65094x family which default to the different values, however currently we are recommending a single solution with I2C changes in order to help customers to stock only one part number. [Edit: additional OTP spins with default voltages have been released].

    3. Intel provides BIOS support for the APL SoC. Customers are recommended to contact their local Intel FAE for full details. My understanding is that Intel will provide the BIOS on the Customer Reference Board (CRB) with TI PMIC (IBL#560683) to customers, but that customers are recommended to use one of the approved BIOS vendors if they would like to customize the BIOS in any way.

    4. The full reference design is only available from Intel. It is IBL#560683. We can provide full datasheet and samples but not the Intel documents.

    5. TPS650941 has been verified on the EVM (available by request) to support 21A DC current from BUCK2 using the CSD87588N FET. Intel has also performed extensive validation on the CRB with this part.

    6. Yes, the controllers have been validated to support down to 4.5V input both for the FET input and the driver input. The datasheet follows the specification dictated to us by Intel, which did not support 5V input. Our part however is capable. The key care about for a 5V application is the VSYS pin on the PMIC. First, the UVLO set by Intel is 5.6V rising, 5.4V falling, so the PMIC will not power on until this voltage is achieved. In order to turn on in a 5V application, we recommend adding a small boost converter to boost 5V up to 5.8V at the input. The current requirement for this pin is about 40 mA max for the PMIC + 200 mA max if using LDO5P0 to power the drivers (not typical in this use case as the 5V is usually applied directly to the driver inputs) + 200 mA max if enabling LDOA1 by I2C (it is disabled by default per Intel request). Secondly, the VSYS voltage needs to rise with the V5ANA, so we are recommending adding a diode to the VSYS pin from the 5V supply to help it rise with V5ANA. Then when the boost comes up, it will rise to the required 5.8V. The boost should have it's own diode if it can't handle precharge and it will need to increase in voltage to account for this diode drop if this is the case.

    7. I have added you to the folder for access.

    Let me know if you have any additional question Liu.