Hello,
The TPS650860 product page shows this part intended for use with Xilinx.
Is there a ZYNQ application / design available?
Patrick
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Hi Patrick,
We are currently in the process of developing a few Xilinx related TI Designs for TPS65086x family, including a couple for the Zynq Ultrascale+ (ZU9EG in this particular design). Due to the high degree of flexibility in the FPGAs we are still trying to decide the optimal default setting for these OTPs and would be interested in hearing your power requirements.
Do you have a specific power map you are targeting? The TPS65086x is typically being targeted for high Vin applications or high current applications while TPS65218 and TPS65911 are used for lower Vin ranges. These both have finished TI Designs (www.ti.com/.../TIDA-00478 and www.ti.com/.../TIDA-00551 respectively).
Hi Kevin,
I have a 9-15VIN design using XC7Z020-1CLG484I and because it has (2) TI AFE5816 requires many rails. 5V (Probe Control), 3V3, 3V15, 2V5, 1V9, 1V8, 1V35 (DDR3L) and VTT, 1V2 and 1V0. Green are FPGA and Bold are AFE8516.
The high current 1-2A are 3V3, 1V8, 1V0. I also have sequencing requirements and so I have a TPS650860 on my desk under evaluation. So far looks like it would work except the 3MHz fixed switch frequency which is in the ultrasound band. 1MHz or lower (I typically run 600 KHz) is best and I sync to the FPGA. But there's always filtering CM Choke and ferrite beads. I will load this evm next week for realistic currents and look with spectrum analyzer at noise (not in datasheet and I must pass FCC B).
The TPS650860 is the only multi-buck with digital control and a vin high enough for 3s3p design that I can find.
Patrick
Hi Patrick,
Thank you for the additional information. Controllers should be fine as far as frequency (they are 1 MHz) but you may need to filter any high Vout converters since they are hysteretic and the Fsw will increase as Vout increases.
One additional note you may be interested in is that the Xilinx reference design we are working on right now uses BUCK2 to generate 3.3V and then feed that back into PVIN3/4/5 and V5ANA. The spec says 4.5V minimum but they were originally designed for 2.5V minimum so we are now validating the 3.3V input to add to datasheet so no external rails are needed.
Will you be using an EC to control the TPS650860 in the design or are you looking to have a custom OTP generated? If looking to go the custom OTP route, then you'll need to work with our marketing team (ipgmkt@list.ti.com).
For this device, the default voltage / sequence are stored in one time programmable (OTP) non-volatile memory that is programmed as part of the chip test procedure. These values can be overwritten once PMIC has power, but will only be stored in volatile registers, so they need to be reprogrammed at each power on.
Let me know if you have any problems working with the EVM, I'm always looking to improve the collateral and make it easier to use.
Kevin,
I overlooked the OTP aspect as I was thinking this was like TPS65911 eeprom or flash based. I could do a small EC.
Is there one typically used for this purpose? Assume this would be low power I2C master on a keep alive circuit.
Patrick
Hi Patrick,
I'm not sure. I've had a project on the backburner for some time to try and program the MSP430 on the EVM to do the voltage / sequence setting but I haven't gotten around to it yet. Overall I suspect it should be pretty simple:
I2C write / read program
On boot:
Write 8 voltages (6xbuck + 2xLDO)
Write first resource on
Wait x ms
Write second resource on
Wait x ms
.
.
.
Write last resource on
Since MSP430 could be powered by always on LDOA1, it would boot when VSYS is available and then PMIC would follow suit.
Kevin,
Is there an EEprom version in the works?
My last design used an LTC2977 and the fault logging has been very good for field issues.
Patrick
Kevin,
Is the MSP430 code avail as a starting point for me?
TPS650860EVM U10 USB2ANY MSP430F5529IPN
Is there another (smaller) part than 80QFP that I could use for this as most pins are N/C?
My VBAT is 9-15VDC.
Thanks,
Patrick