TPS65251

Here the answers:

.       The datasheet mentions the following on the first page (second paragraph from the bottom):   TPS65251 features a supervisor circuit that monitors each converter output. The PGOOD pin is asserted once sequencing is done, all PG signals are reported and a selectable end of reset time lapses. The polarity of the PGOOD signal is active high.  How does one set the “selectable end of reset time”?.  It is not covered in the datasheet.  Jeff would like to use this to hold the processor in reset until the rails are stable.  If one of the rails drops out of regulation, he wants to hold the processor in reset for a minimum period. 

For the catalog part TPS65251 the reset time is 1s (fixed) after all rails are powered up and the PG flag (internal) is asserted.

2.       What is the threshold voltage for the EN (enable) pin?  I assume it is around 1.3V, but the datasheet doesn’t specify it

From latest spec

.

3.       What is the availability of the device?  TI website shows it as Active and samples can be requested.

RTM process is on-going, pedro can update you on this.  Samples and EVMs can be supplied directly from our group.

On Page 13 (Overview) it says, “The device has two built-in LDO regulators. During a standby mode, the 3.3-V LDO and the 6.5-V LDO can be

used to drive MCU and other active loads.”

How much current can these LDO’s source to external loads? The electrical Characteristics table on page 6 specifies the output voltages, but not the currents.

We suggest not to go beyond 10mA (see attached foils).

Also, as we noted yesterday the datasheet doesn’t contain any information about power down. I assume from this that when a converter is “shutdown” due to either an over-current or UVLO condition, the high side FET is shut-off, and the output voltage is simply allowed to decay through the load. But, what is done with the low side FET? Is it turned-on or off? I’m not sure if this really matters, but I worry about oscillation if it is turned-on during shut-down and the load is too light to damp the resulting tank circuit formed by the output inductor and capacitors. This could also be an issue if I back feed the 1.8 V rail from the 3.3 V rail during shutdown to ensure that 2 V differential is not exceeded.

On power-down both fets are switched-off.  Device relies on feedback chain resistors to discharge output

All that said, I think I can make this part work for me with the following configuration.

1. Floating the 1.2 V supply enable pin so it starts as soon as 12 V is applied to Vin.

There is a 10ms delay from the time when Vin UVLO is asserted to the time converter starts

2. Delay the 1.8 V power-up by placing a cap on its enable pin, so it comes up after the 1.2 V rail.

OK

3. Connect the 3.3 V enable pin to the 1.8V rail through a voltage divider and place a cap on its soft-start pin to ensure it comes up after the 1.8V rail and is shut-off whenever the 1.8V drops below 1.6-1.5 V.

That just leaves ensuring that 3.3 V – 1.8 V is always less than 2 V during power-down. I think I can do that by either engineering the decay rates to maintain that difference under different loading conditions, or by placing a 1.9 V LDO between the 3.3 V and 1.8 V rails.

Here the answers:

1.  For the catalog part TPS65251 the reset time is 1s (fixed) after all rails are powered up and the PG flag (internal) is asserted.

2.      Found in latest spec

3.   RTM process is on-going, pedro can update you on this.  Samples and EVMs can be supplied directly from our group.

      4. We suggest not to go beyond 10mA (see attached foils).

      5.  On power-down both fets are switched-off.  Device relies on feedback chain resistors to discharge output

All that said, I think I can make this part work for me with the following configuration.

1. Floating the 1.2 V supply enable pin so it starts as soon as 12 V is applied to Vin. There is a 10ms delay from the time when Vin UVLO is asserted to the time converter starts
2. Delay the 1.8 V power-up by placing a cap on its enable pin, so it comes up after the 1.2 V rail. OK