TPS65217: TPS65217 output waveform before 50ms

TS Yang

Part Number: TPS65217

Hi,

I'm testing with TI's TPS65217 for our bill-counter application, and measured the input & output waveform as attached.

After supply the power, the waveform before 50ms looks transitional, and I'm not sure this waveform is normal or not.

I think the number and capacity of capactiors at the SYS output influence, so if you have any documents about SYS output caps, please share for me.

below is waveforms.

1) AC input

2) LDO4 output

3) SYS output

thanks,

over 7 years ago

0 TS Yang over 7 years ago

Genius 4800 points

FYI,

I refer to the TPS65271C EVM user guide for output capacitors.

( http://www.ti.com/lit/ug/slvu580b/slvu580b.pdf )

I use DCDC1,2,3 input (pin 21,22,32) capacitor as 10uF, SYS output (pin 7,8) capacitor as 22uF.

As I mentioned above, I need the recommended number and capacity of capactiors besides the EVM reference cap value .

0 Tuan Tran74 over 7 years ago in reply to TS Yang

TI__Genius 17670 points

Hi TS,

In section 10.2 page 73 of the specification the typical block diagram shows one 10uF at the input of each DCDC switching regulators in addition to one 22uF at the SYS pin. The waveform will have some transitional periods where all the interal supply powers up upon first AC voltage being applied and time for us to sense that AC votlage is good then we switch the voltage on AC to SYS.

Thanks Tuan

0 TS Yang over 7 years ago in reply to Tuan Tran74

Genius 4800 points

Hi Tuan,

thanks for your answer.

As your reply "The waveform will have some transitional periods where all the interal supply powers up upon first AC voltage being applied and time for us to sense that AC votlage is good then we switch the voltage on AC to SYS." , I understand that we need 50ms time just after power up.

However, my question is about "0~110ms period, why below two waveform is different, and which one is normal?"

I'm looking forward for your answer for this.

thanks,

0 Tuan Tran74 over 7 years ago in reply to TS Yang

TI__Genius 17670 points

Hi TS,

From scope capture 1 above the initial condition for SYS is above 0V and for scope capture 2, SYS is at 0V. What this is telling me is that AC input was not at ground or removed long enough for all node voltages to discharge to be the same initial condition. You might want to look at INT_LDO and BYPASS to see if the initial conditon for both case is the same. But the reason they are different can be different initial condition.

Thanks Tuan

0 TS Yang over 7 years ago in reply to Tuan Tran74

Genius 4800 points

Hi Tuan,

The initial condition of SYS what you said is due to repeated process of turn off for testing and supply power again in a short period of time.
When fully turn on power in a discharged state then the same voltage will start from zero v.

It doesn't seem to be relevant to what I'm talking about.

Again, I'm requesting a review that the reason why the LDO4 and SYS waveform is would not rise vertically as EVM, before the LDO4 output coming to the 3.3V

Also, please review above scope capture 1 and 2 that why they are different.

That's about it.

0 Tuan Tran74 over 7 years ago in reply to TS Yang

TI__Genius 17670 points

Hi TS,

Below is what we see on the TI evaluation board and that's what we would expect if there is no external loadings. Can you provide a schematic to us? We would like to see how you are using the part.

Thanks Tuan