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TPS65311-Q1: WD_RESET

Part Number: TPS65311-Q1

Hi,

I would like to confirm the operation when WD_RESET.

When WD RESET happens seven times, TPS65311 moves into LPM0 mode.

So the TPS65311 remains active mode when WD_RESET happens lower six times.

Because the Nres acchive 7.

Is my understanding correct?

Best Regards,

Kuramochi

  • Kuramochi-san,

    Thanks for the post! Your understanding is correct. Barring that there are no other reset events in the system, the device will remain in the active state if WD_RESET happens 6 times because the Nres threshold is set at 7. Please let me know if there are any questions. Thanks! 

    Regards,

    Paul Kundmueller

  • Hi Paul-san,

    My customer says that the output voltage remains though they eliminate WD signal during a few minutes.

    Could you confirm followings;
    - How long does it take to increment EC?
    - How long does it take to move to LPM0 from eliminating WD signal?

    Best Regards,
    Kuramochi
  • Hi Kuramochi-san,

    After WD signal is taken off, device waits until WD window time (20ms typ) and RESN is pulled low and error counter is incremented (EC=1). RESN is pulled low for RESN hold time (2ms typ) duration and RESN goes up again. From this rising edge of RESN, WD Timeout duration starts (300ms typ). If WD pulse is not detected within this time, RESN goes low again and EC get incremented again (now EC=2). This continues until EC=7 and once EC=7, device goes in to LPM0 mode and GPFET gets disabled.

    So, with this we can calculate the typical time duration for device to get in to LPM0 mode after WD pulse is taken out:

    20ms (initial WD window time )+ 2ms*6 (RESN hold time) + 300ms *6 (WD Timeout ) = 1832ms

    I have attached one waveform showing the effect of WD pulse removal on the device RESET pins (RESN, PRESN, IRQ) and VINPROT voltage. As soon as RESN goes down for 7th time, device gets in to LPM0 mode and VINPROT starts to go down. This waveform almost matches with my above calculation.

    I think that the time taken for EC increment after detection of WD reset event will be less than 20us, but this time is negligible compared to the other larger time duration.

    Depending on their output load current and capacitors, it may be possible that output voltages stay high for longer duration until output capacitors are discharged. They can check this by applying some dummy load on outputs.

    Hope this answers your question.

    Regards,

    Murthy