In a design I am implementing the TPS65910AA1 with the Sitara processor. I have a few question on the RTC when using an external Crystal or internal OSC. The Boot mode for this processor is BOOT[1:0]=1,0.
The 2 documents I am referring to are: SWCU093, boot mode 1,0 for the AM335x and the document SWCS046 for the TOP device definition.
Questions:
1) Document SWCU093 states in Table 2 (EEPROM CONFIGURATION...), for VRTC_REG that the device will be low-power mode in the OFF state. What is the difference when in SLEEP-LOW-POWER and when OFF-LOWPOWER?
2) When in in the BACK-UP state, are the RTC registers and registers that influence the RTC powered: RTC_CTRL_REG, COMP_REG, VRTC_REG, DEVCTRL_REG? Document SWCS046U seems to state that only the RTC clock is powered and all other registers are in RESET state (6.3.1 State-Machine). If so, then when in backup mode with backup battery, how are the following being maintained:
a) When running from the internal RC OSC, if the RTC compensation Registers are not maintained, how is the proper time kept? Or are Backup the compensation registers reset to 0 and accurate time is not kept?
b) What is meant (in SWCS046 6.3.1 State-Machine) "in RESET STATE"? Does this imply the EEPROM settings, as defined in document SWCU093, are reloaded into the Registers as defined in SWCU093 EEPROM table or is the Reset State as defined for each register as defined in SWCS046 Register table?
c) So when in BACKUP state, if the register values are not maintain (not powered), is it correct to assume the choice of the RTC source CLK (internal or external) can only be the default RESET choice? For my application, when in BACKUP state, would my source clock selection be determined by:
i) the default as define in SWCU093 (BOOT MODE[1:0] = 1,0), as stated in the Table 2 EEPROM Config table, DEVCTRL_REG/CK32K_CTRL = internal RC? or
ii) the default as defined in SWCS046 Table 6-51 DEVCTRL_REG/CK32K_CTR, = internal RC?
ii) when entering backup state are the SWCU093 EEPROM values reloaded into the registers, or are they placed in the RESET valves as defined in register map in doc SWCS046?
iii) is it possible while in backup to have the external crystal used as the RTC Clock source? This is what I desire
iiii) Is it possible while in backup to have the RTC clock be compensated with the compensation registers?
d) what is meant by "Clock gating of RTC register and logic, low-power mode" in DEVCTRL_REG / RTC_PWDN definition?
e) During what state transition(s) are EEPROM values loaded into the registers?