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TPS65910: TPS65910AA1: RTC Clock source and Register Retention when in BACKUP State

Part Number: TPS65910

In a design I am implementing the TPS65910AA1 with the Sitara processor. I have a few question on the RTC when using an external Crystal or internal OSC. The Boot mode for this processor is BOOT[1:0]=1,0.

The 2 documents I am referring to are: SWCU093, boot mode 1,0 for the AM335x and the document SWCS046 for the TOP device definition.

Questions:

1) Document SWCU093 states in Table 2 (EEPROM CONFIGURATION...), for VRTC_REG that the device will be low-power mode in the OFF state. What is the difference when in SLEEP-LOW-POWER and when OFF-LOWPOWER?

2) When in in the BACK-UP state, are the RTC registers and registers that influence the RTC powered: RTC_CTRL_REG, COMP_REG, VRTC_REG, DEVCTRL_REG? Document SWCS046U seems to state that only the RTC clock is powered and all other registers are in RESET state (6.3.1 State-Machine). If so, then when in backup mode with backup battery, how are the following being maintained:

a) When running from the internal RC OSC, if the RTC compensation Registers are not maintained, how is the proper time kept? Or are Backup  the compensation registers reset to 0 and accurate time is not kept?

b) What is meant (in SWCS046 6.3.1 State-Machine) "in RESET STATE"? Does this imply the EEPROM settings, as defined in document SWCU093, are reloaded into the Registers as defined in SWCU093 EEPROM table or is the  Reset State as defined for each register as defined in SWCS046 Register table?

c) So when in BACKUP state, if the register values are not maintain (not powered), is it correct to assume the choice of the RTC source CLK (internal or external) can only be the default RESET choice? For my application, when in BACKUP state, would my source clock selection be determined by:

i) the default as define in SWCU093 (BOOT MODE[1:0] = 1,0), as stated in the Table 2 EEPROM Config table, DEVCTRL_REG/CK32K_CTRL = internal RC? or

ii) the default as defined in SWCS046 Table 6-51 DEVCTRL_REG/CK32K_CTR, = internal RC?

ii) when entering backup state are the SWCU093 EEPROM values reloaded into the registers, or are they placed in the RESET valves as defined in register map in doc SWCS046?

iii) is it possible while in backup to have the external crystal used as the RTC Clock source? This is what I desire

iiii) Is it possible while in backup to have the RTC clock be compensated with the compensation registers?

d) what is meant by "Clock gating of RTC register and logic, low-power mode" in DEVCTRL_REG  / RTC_PWDN definition?

e) During what state transition(s) are EEPROM values  loaded into the registers?

  • Hi Eric,

    Your question has been assigned for product expert.

    Best regards,
    Jari Niemelä
  • Hi Eric,

    Below are the answers to the questions you asked about the TPS65910 RTC and backup states:

    1. SLEEP-LOW-POWER and OFF-LOW-POWER have the same effect on the VRTC pin. There is no difference between these two modes for this pin since this pin maintains its value. Low power mode is the same as back up mode.

    2. When in backup state, the RTC registers are all maintained. Thus, there is no issue with keeping time or using the external crystal.

    3. When in RESET state, the registers will enter reset state as defined by the data sheet (SWCS046). Then, when the device changes to ACTIVE mode, the EEPROM settings are loaded as defined by the user guide (SWCU093).

    4. Clock gating of the RTC register and logic is a feature that allows the RTC to decrease dynamic power consumption while in low power mode.

    Let me know if you have any further questions!

    Thanks,
    Nastasha
  • Nastasha,

    Thanks for your help!

    My goal is understand if RTC clock source can be an external Crystal while in BACKUP mode? and while in backup mode RTC configurations do not change. I am observing that when the system in powered on the RTC keeps time accurately but when power powered down, some systems gain time while other system lose time. Observing about 5 min per day gain or loss. I can only theorize that while in backup, the internal OSC is switching into the mix. The internal OSC has a large tolerance.

    1)From Document: Backup: The main battery supply voltage is high enough to enable the VRTC domain but not enough to
    switch on all the resources. In this state, the VRTC regulator is in backup mode and only the 32-K
    oscillator and RTC module are operating (if enabled).

    Are the following Registers considered part of the RTC module?
    RTC_CTRL_REG, RTC_STATUS_REG,RTC_COMP_LSB/MSB_REG, RTC_RES_PROG_REG, RTC_RESET_STATUS_REG,
    and DEVCTRL_REG, VRTC_REG,

    2) Can you provide information on auto calibrate? Are calibration registers only implemented when using the internal Osc or can they be used with an external Crystal? How would SW calculate these calibration values for each unit?

    3) you mentioned the Reset state, but the state diagram does not depict a RESET state. Can you explain when registers are set to their reset values ? Also the state diagram depicts that to transition from Backup to the Active state, first, a transition to the off state is required. When entering the off state are some registers set to there reset values?

    Thanks.
  • Eric,

    The RTC clock source can be an external crystal while in BACKUP mode. All the registers you mention (that begin with "RTC") are included in the RTC module and therefore should be kept operating while in BACKUP mode.

    Auto calibrate allows you to compensate for drift. It can be used with the internal or external clock. If you can estimate your time drift in one hour, you can use that value as your compensation. This function (when enabled) would then apply your estimated time amount within each hour.

    When going from BACKUP to ACTIVE, the device does turn off, thus enabling a reset as it goes into ACTIVE. The RTC and BACKUP registers are maintained through this process. All other registers are set to their reset values before the device enters ACTIVE mode, but it cannot be determined exactly when that occurs.

    Please let me know if there is anything else I can assist with!

    Best,
    Nastasha