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TPS65311-Q1: Write register during LPM0 mode

Tomoaki Yoshida
Expert 2200 points
Part Number: TPS65311-Q1

Hi,

I have a qustion.

Is register write possible in LPM0 mode?

If possible, will all registers be retained when returning from LPM0 mode?

Best regards,

Tomoaki Yoshida

  • 0
    TI__Expert 5600 points
    Hi Tomoaki,

    Thanks for your post. I have assigned the thread to the expert on this device.

    Best regards,
    Jari Niemelä
  • 0 in reply to Jari Niemela13
    TI__Expert 8730 points

    Hi Tomoaki-san,

    In LPM0 mode, all the regulators will be shutdown except DVDD and I do not think that any SPI write is possible in this case. VIO is needed for SPI communication and typically at system level, VIO is supplied by one of the regulator outputs (of TPS65311).

    Regarding the register settings retention in LMP0 mode, I will get back to you before end of next week as currently we have some public holidays and vacation times. I want to reconfirm this on the EVM and check with design team before providing the feedback.

    Can you please let me know more details about this project like: Customer, Application and project status? You can email this information to me at: kmurthy.hegde@ti.com

    Regards,

    Murthy

  • 0 in reply to Krishnamurthy Hegde
    TI__Expert 8730 points

    Hi Tomoaki-san,

    Regarding the SPI register retention in LPM0 mode, please see below.

    - In LPM0 mode, EC and EC_OF retains their value and other registers are reset to their default value. But EC_OF flag is cleared as soon as this register is read during Active Mode
    Hope this helps you. Can you please send me the details about this project?

    Regards,

    Murthy