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TPS65217: PPATH Current Sensing Timing

Part Number: TPS65217

I have a customer who is asking the following question:

What is the behavior and reaction time of the PPATH input when the Vsys load exceeds the PPATH current setting for the TPS65217?

Example - 5V AC power is applied, battery and USB power is NOT applied, the IC completes the power up sequence, IAC is set to "01" (the 500mA limit) and later Vsys is shorted to PGND (or exceeds the 580mA max limit by 1mA for a 1us).  Does the AC input disconnect from the Vsys pin and if so how quickly?  

Is the behavior the same for the USB input (no other power input applied)? For the Battery input (no other input power applied)?

Thanks for your help with this questions.

Richard Elmquist

  • Hi Richard,

    I have assigned this request to concerned Applications Engineer and we will get back to you as soon as possible.

    Regards,

    Murthy
  • Murthy,

    Thanks for your help with this!

    I am looking forward to your response.

    Richard Elmquist

  • Richard,

    The behavior is a little bit more complex than the customer may expect. Generally speaking: IAC, IUSB, and IBAT are all set to different thresholds and the output current from AC/USB is dependent on both ISYS and IBAT (positive or negative depending on if the battery is charging or discharging).

    See Figure 11 in the datasheet for an image depicting this use case.

    Now, AC and USB should not both be enabled at the same time. And in your customer's use case it says that VAC is applied but both USB and BAT are NOT applied. Please help me understand the last part of this question if "battery and USB power is NOT applied".

    "Is the behavior the same for the USB input (no other power input applied)? For the Battery input (no other input power applied)?"

     

    Regarding the AC to SYS path only, assuming no battery, the IAC current limit time is not specified in the datasheet. The best answer I can give would be by testing it personally and reporting back the results. However, this answer will not necessarily apply to all units of the TPS65217. It will be a nominal test at room temperature on a single unit.

  • Brian,

    Thanks for your response!

    I will let you know if the customer requests the test or if they have any further questions.

    Thanks for your help with this!

    Richard Elmquist

  • Brian,

    The customer has asked a further question:

    Thank you for the response, Figure 11 is not quite what I was getting at - I want to understand what the behavior(and response time for the behavior if it was available from inspecting the design) is when only one of 3 inputs is powered (all other inputs are disconnected/floating), and current through that input (delivered to the Vsys pin) exceeds the specified limit?

    I assume the IC limits the current; how – it shuts the input down Vsys, or resistance of the ideal diode OR increases to try to maintain current below the limit or something else?

    Can you answer his question with the new information that he sent?

    Thanks for your help with this!

    Richard Elmquist

  • Brian,

    Have you been able to look at the customer's further questions?

    Thanks for your help with this!

    Richard Elmquist

  • Richard,

    The resistance of the FET will increase to decrease the load current to the limit set-point. Therefore, the VSYS voltage will drop as the resistance increases.

    This will occur up to a certain point and is referred to as soft-limiting.

    The hard-limiting protection will kick in later and will shut off the FET completely. This will look like an entire system reset.

    Do you need more details?

  • Brian,

    Thanks for your response!

    I will let you know if the customer has any further questions.

    Thanks for your help.

    Richard Elmquist