TPS659122EVM-081: Issue to initial the DCDC power of TPS659122 PMU

Part Number: TPS659122EVM-081

Hi greeting:

We're under help our customer to debug the TPS659122 with Tof sensor (OPT8320)  application.

They've feedback a problem about the voltage abnormal case when sending the code to call the register: 0x0Ah (DCDC3_OP), fail rate about 11/60 pcs and cant be duplicated

Through the I2C to call the DCDC Register memory map, it will get non-ack information, but get acknowledge OK when sending again. It always happened when set dcdc3_op this one.

We'd like to know is there anything suggestion to customer check their coding? or some point we could check again? 

1. customer schematic

2. code

 3. compare the I2C information between pass & fail status.

8 Replies

  • Kay,

    I have assigned this post to the expert on the TPS659122 and she will respond to your inquiry as soon as possible.
  • Hi,

    Since the NACK occurs just after the read/write request, I would check the previous write command. Maybe try swapping the order of your I2C instructions to see if the problem still occurs.

    Let me know what results you find or any further questions you may have.

    Thanks,

    Nastasha

  • In reply to Nastasha:

    Hi Nastasha:

    Thanks again, maybe you could also help us to suggest the command whether has the problem or not (pasted as following)

    basically follow-up the original code format.

    UCHAR TPS65912_REG[][2] = {
    {DCDC1_AVS, 0x00},
    //{DCDC2_AVS, 0x00},
    //{DCDC3_AVS, 0x00},
    {DCDC4_AVS, 0x00},

    {LDO1_AVS, 0x00},
    {LDO2_AVS, 0x00},
    {LDO3_AVS, 0x00},
    {LDO4_AVS, 0x00},
    {LDO5, 0x00},
    {LDO6, 0x00},
    {LDO7, 0x00},
    {LDO8, 0x00},
    {LDO10, 0x00},

    /* DCDCx_CTRL, set for slowest ramp */
    {DCDC1_CTRL, 0x1C},
    {DCDC2_CTRL, 0x1C},
    {DCDC3_CTRL, 0x1C},
    {DCDC4_CTRL, 0x1C},

    // set dcdc1_op : selreg =1 , will control AVS registers
    // 1.5V
    {DCDC1_OP, 0x68},
    {DCDC1_AVS, 0xA8},
    {DCDC1_LIMIT, 0xBF},

    // set dcdc2_op : selreg =1 , will control AVS registers
    // 1.8V
    {DCDC2_OP, 0x74},
    {DCDC2_AVS, 0xB4},
    {DCDC2_LIMIT, 0xBF},

    // set dcdc3_op : selreg =1 , will control AVS registers
    // 3.3V
    {DCDC3_OP, 0x78},
    {DCDC3_AVS, 0xB8},
    {DCDC3_LIMIT, 0xFF},

    // set dcdc4_op : selreg =1 , will control AVS registers
    // 1.6V ~ 2.0V
    {DCDC4_OP, 0x6F},
    {DCDC4_AVS, 0xAF},
    {DCDC4_LIMIT, 0xBF},

    // set LDO1_op : selreg =1 , will control AVS registers
    {LDO1_OP, 0x46},
    {LDO1_AVS, 0x86},
    {LDO1_LIMIT, 0x1F},
    // set LDO2_op : selreg =1 , will control AVS registers
    {LDO2_OP, 0x44},
    {LDO2_AVS, 0x84},
    {LDO2_LIMIT, 0x1F},
    // set LDO3_op : selreg =1 , will control AVS registers
    {LDO3_OP, 0x7F},
    {LDO3_AVS, 0xBF},
    {LDO3_LIMIT, 0x3F},
    // set LDO4_op : selreg =1 , will control AVS registers
    {LDO4_OP, 0x40},
    {LDO4_AVS, 0x00},
    {LDO4_LIMIT, 0x00},
    {LDO5, 0x00},
    {LDO6, 0x00},
    {LDO7, 0xB2},
    {LDO8, 0x88},
    //{LDO9, 0x00},
    {LDO10, 0x90},

    //enable the load switch
    {LOADSWITCH, 0x0D},

    //enable the LEDs
    {GPIO3, 0x40},
    {GPIO4, 0x40},
    {GPIO5, 0x40},

    //dc current of 2ma, no ramp
    {LEDA_CTRL1, 0x00},

    //T1-- LED: seq time is zero. set nayone to some value
    {LEDA_CTRL2, 0x0F},
    {LEDB_CTRL2, 0x0F},
    {LEDC_CTRL2, 0x0F},

    //set the ON duty cycle 100 %
    {LEDA_CTRL7, 0x1F},
    {LEDB_CTRL7, 0x1F},
    {LEDC_CTRL7, 0x1F},

    //set the on time < seq time
    {LEDA_CTRL8, 0x0C},
    {LEDB_CTRL8, 0x0C},
    {LEDC_CTRL8, 0x0C},

    //ramp up ramp down times are zero
    {LED_RAMP_UP_TIME, 0x00},
    {LED_RAMP_DOWN_TIME, 0x00},

    //configure to enable LED
    {LED_SEQ_EN, 0x70},

    };
  • In reply to Kay Chen53:

    Kay,

    I will look into testing this code on the bench and get back to you after my tests.

    Thanks,
    Nastasha
  • In reply to Nastasha:

    Kay,

    I used your code on my EVM and I cannot replicate the issue you are having. Have you tried running your code in a different order? Let me know if you have any results.

    Thanks,
    Nastasha
  • In reply to Nastasha:

    Dear Nastasha:

    Thanks for your replay, I'll also check this with customer side; in another hand, will it helpful to add the delay or check the timing for the I2C interface?

    any known issue could reference for kind of issue?

    Thanks again.

    B&R
  • In reply to Kay Chen53:

    Kay,

    I am unaware of any issues with I2C reads and writes. You can try adding delays, but I do not know that it would change the outcome.

    Thanks,
    Nastasha
  • In reply to Nastasha:

    Dear Nastasha:

    Due to customer product running under 400KHz frequency, I'll try to suggest them adding the t(BUF) > 66us bus-free waiting time for each command.

    Thanks again.