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TPS65911: VIO IS WAY TOO HIGH AND CAN'T CHANGE IT

Part Number: TPS65911
Other Parts Discussed in Thread: TLV320AIC3101, DM385, DM388

I am using the TPS6591133 to power a DM385. I am only using the VIO to power the DVDD_C, VDDA_1P8, VDDA_PCIE_1P8, VDDS_OSC0_1P8, VDDS_OSC1_1P8 of the DM385 and the DVDD of a TLV320AIC3101 audio CODEC. I have verified before getting the board booted that the VIO was 1.8V

I have had 2 boards now have the VIO go up to 3.5V even though the register setting was for 1.8V. When we tried to change it the only setting that works is 3.3V or off. Any of the other settings do nothing an the output stays at 3.5V.

I removed the output EMI filter to isolate it and see if it was the PMIC or something driving it. The output went to 4V with no load so I put a 100 OHM resistor in for a load and it still was 4V. All the other voltages are correct and can be changed.

What would cause this to happen? Any help or ideas would be great.

  • Brain,

    It looks like the feedback trace is not connected correctly or some external rail is driving the output high. It would be helpful if you can provide schematic and switch node and output ripple waveform before and after bootup to help debug the issue.

    Jay
  • The VIO outputs the correct voltage at first but somehow along the way it goes up to the 3.5V. I have confirmed the feedback is correct on the board layout. For the schematic I copied the DM388 Camera Start Kit eval board that uses the TPS6591133. Literature number SPRUIC7. I will post the picture of the startup later.

    After I made this post I checked the startup sequence and found that it does not startup in the correct order even though I have the Boot pin tied to VRTC. Here is the boot order:

    Note: Each boot sequence is 2ms from each other unless noted on the right

    VRTC
    VIO 4ms after VRTC
    LDO8
    LDO4
    LDO3&6 4ms after LDO4
    GPIO0
    LDO5&7
    GPIO7 1.75ms after LDO5&7
    LDO1&2 2ms after LDO5&7
    VDDCRTL 2.5ms after LDO1&2
    VDD1 1.5ms after VDDCTRL
    VDD2
    NRESPWRON 4ms after VDD2
  • I got the document wrong. Its the DM388 CSK Document Number MS_TI_TMDXCSK388_SCH_REVA. That is the schematic I used to design my board.
  • Can you please send me scope shot of VIO switch node and vout ripple. Also can you disconnect the load from VOUT and check if VOUT voltage changes. Also please confirm if VIO register value does not change when output voltage change from 1.8V to 3.5V.

    Regards,
    Jay
  • I have the screenshots but I can't seem to find a way to attach them to this post. Do you have an email I could send them to?

    When I disconnect it from the load it goes to about 4V regardless of register setting except the 3.3V setting.

    The register in the PMIC is set for 1.8V. In fact the only register setting that works is the 3.3V setting. All others just output the 3.5V
  • Brian, if you select "Use rich formatting", it will provide a mechanism to attach files.
  • Brain,

    Can you please check when VCC6 voltage comes up. In the sequence you have sent, it looks like VCC6(3.3V) is high only after GPIO7 is high which is wrong. This would cause LDO1 and LDO2 to power up wrong.

    Also can you disconnect the resistor between TPS_VDDA_1V8 net and VDDA_1V8 to check if the votlage is still shoots to 3.5V. Also, I would try to change voltages on other rails to check for feedback path between rails.

    Regards,

    Jay

  • Jayanth,

    Good call on the VCC6. I am feeding it with the 3.3V that GPIO7 is turning on which explains the sequence mix up. We are trying to hack in a fix for this to see what else it might fix but I think the raised VIO voltage is a separate issue. I will post the results if we can get the board to work after our fix.

    I have an EMI filter that is directly on the output of VIO that I have removed to check VIO when disconnected from the circuit. VIO actually rises to 4V when removed from the circuit. 

    We have successfully changed VDDctrl to 1.35V. Do you need me to try a different one? 

    Thank you,

  • Hi Brian,

    Does clearing DCDCCKSYNC in DCDCCTRL_REG (address 0x3E) have any effect?

    Best Regards,

    Rick S.

  • Hi Rick,

    I'm helping with this project and just tried setting register 0x3E to 0x00, however it did not seem to fix the issue. Here's what I did, let me know if I should have done something different:

    First, I dumped the registers using i2cdump:

    i2cdump 1 0x2d
    No size specified (using byte-data access)
    WARNING! This program can confuse your I2C bus, cause data loss and worse!
    I will probe file /dev/i2c-1, address 0x2d, mode byte
    Continue? [Y/n]
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 00 00 00 01 01 00 00 00 00 00 00 01 01 00 00 00    ...??......??...
    10: 00 80 00 00 00 27 00 00 00 00 00 00 1f 01 01 00    .?...'......???.
    20: 05 0d 33 33 0d 33 33 01 33 33 00 00 00 00 00 00    ??33?33?33......
    30: 51 51 65 29 65 65 51 65 0d 00 00 00 00 00 39 34    QQe)eeQe?.....94
    40: 34 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f    4..............?
    50: 02 fd 88 ff 4a ff 00 00 00 00 00 00 00 00 00 00    ???.J...........
    60: 07 08 05 08 08 08 05 07 08 00 20 00 00 00 00 00    ?????????. .....
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    80: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............
    90: 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00    .?..............
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    

    Next, I used i2cset to clear the specified register:

     i2cset 1 0x2d 0x3e 0x00
    WARNING! This program can confuse your I2C bus, cause data loss and worse!
    I will write to device file /dev/i2c-1, chip address 0x2d, data address
    0x3e, data 0x00, mode byte.
    Continue? [Y/n]
    

    And then I re-dumped the registers to make sure the write took effect, which it did:

     i2cdump 1 0x2d
    No size specified (using byte-data access)
    WARNING! This program can confuse your I2C bus, cause data loss and worse!
    I will probe file /dev/i2c-1, address 0x2d, mode byte
    Continue? [Y/n]
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 00 00 00 01 01 00 00 00 00 00 00 01 01 00 00 00    ...??......??...
    10: 00 80 00 00 00 27 00 00 00 00 00 00 1f 01 01 00    .?...'......???.
    20: 05 0d 33 33 0d 33 33 01 33 33 00 00 00 00 00 00    ??33?33?33......
    30: 51 51 65 29 65 65 51 65 0d 00 00 00 00 00 00 34    QQe)eeQe?......4
    40: 34 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f    4..............?
    50: 02 fd 88 ff 4a ff 00 00 00 00 00 00 00 00 00 00    ???.J...........
    60: 07 08 05 08 08 08 05 07 08 00 20 00 00 00 00 00    ?????????. .....
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    80: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............
    90: 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00    .?..............
    a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    

    We checked the voltage before and after setting the value with a multimeter (and the output was "isolated from the network" according to Brian) however we saw no change in voltage.

    Hope this helps

  • Thanks Mikael,

    Well it was worth a shot, additionally you could try writing a value of 0x38 to clear only the DCDCSYNC bits, but if clearing the whole register didn't work I'm doubtful that will fix the issue. A value of 0x00 forces all regulators into PWM mode, so now we also know the issue occurs in PWM mode too.

    At this point I would recommend swapping the part to a known good board, and re-populating the failing board with a known good part. If the issue follows the IC there's a chance it could have been damaged, but if the issue still occurs on the failing board, there could be a system issue.

    Best Regards,
    Rick S.

  • We were able to fix the sequence issue with putting 3.3V at the startup on VCC6 but it did not resolve the issue with VIO.
  • we have 5 prototypes made and all 5 are having this issue with VIO. We have swapped out PMIC's as well and the problem persists. I am going to try swapping out the PMIC and isolating VIO from the rest of the board to see if VIO comes up too high with no load
  • Jay And Richard,

    I have swapped out the PMIC for a brand new PMIC and disconnected VIO from the rest of the board. The VIO output goes to 3.9V when not connected to the processor. This narrows it down to the inductor, Output caps or board layout.

    I have rechecked the input, output and component specs and VIO meets these requirements. Any pointers would be extremely helpful.

    Thank you,
  • Here is the VIO section of my schematic. 

    I have removed C126 to isolate VIO and it is still 3.5-3.9V. 

    The Vsys_5V is also feeding VDD1, VDD2 and VDDctrl and they are working perfectly and changeable. Do I need to change this to 3.3V to be closer to VDDIO?

    The 3.3V feeding VDDIO is the same 3.3V that requires GPIO7 to go low to enable it. Do i need to change this to the same supply that feeds VCC6 so they will be 3.3V at startup?

  • Hi Brian,

    Fortunately the VIO regulator does not have VDDIO dependencies. VIO is often used to supply VDDIO but it can regulate independently.

    Could you verify the feedback path to VFBIO is unaffected in the layout?

    Also, if you are using separate GND planes for the supplies could you confirm that the GNDIO pins have some path back to DGND?

    Best Regards,
    Rick S.
  • Hello Richard,

    I am not sure what you mean by unaffected? I have confirmed that H8 is tied directly to the inductor and I have 2 screen shots of what the output looks like in previous replies. Little to no noise but has an odd stairstep at less than a volt. I have used an ohmmeter to check continuity between H8 and other traces and none of them are connected.

    The PMIC only uses Digital ground and we have not separated the ground planes for it. You can see in my schematic clip that all the ground use the same symbol.

    Thank you,
  • The continuity test resolves the largest concern of possible shorts between closely routed nets. I'm not sure if the offset could be caused by coupling from a nearby aggressor, but it could be related to a non-ideal ground path.

    When you enable and disable the VIO regulator, do the rising and falling waveforms have consistent profiles?

    Best Regards,
    Rick S.
  • I have sent Will Jarret @ TI the PCB layout file under NDA so if you want to check out the ground path's please do. If you see any errors please let me know and we will get them fixed on the next board rev.

    I will check the VIO after an enable or disable and post the screenshots.
  • Here are the screenshots of the disconnected VIO line being enabled and disabled.

    Something we noticed when we disabled the VIO the current draw went down by 170mA. That seems like a lot since the VIO is not connected to a load.

  • Hi Brian,

    It appears that the traces for the VIO switch node pins are not on the same layer, but are for the other regulators. Can you also get a scope shot of the VIO switch node and compare to the known good regulators?

    If VIO's switch node does not look clean you may have reroute those pins.

    Best Regards,
    Rick S.
  • Hello Richard,

    You may have found the issue. Here are the screenshots from the switching side of the inductor:

    VDDCTRL

    VDD1

    VDD2

    VIO

    We will be trying to prove this but it is a VERY difficult modification so the results might take a bit.

    Thank you,

  • Not sure what happened but this is actually the screenshot for VDDCTRL

  • HEllo Richard,

    Sorry it has taken so long to get back to you. We ran out of PMIC's and had to get some shipped. We have confirmed that the switch trace is not the issue. Our tech removed the land pads for K7 and K8 and cut the trace and then flowed a wire to connect the balls to the trace completely cutting out the trace that goes to the bottom layer. VIO is sitting at 3.4V.

    Would you like me to send you the exact list of parts we are using to see if that might be an issue?

    THank you,

  • Hi Brian,

    I'm not sure what I could tell with the components list alone, but a schematic might be helpful for interpreting the layout.

    Ultimately this looks like a failing high side FET, or some how there's a path we're not seeing from VSYS to the SW node of VIO. Does the switch node look the same on this modified layout?

    Would it be possible to capture switch node during the window where it regulates at 1V before it rises to 3.4V? Is there any correlation to this transition period and LDO8?

    Best Regards,
    Rick S.
  • I have sent the full schematic to Will Jarret. It was done using Cadstar. I also gave him the PDF version.
  • Thanks Brian,

    After you modified the board did you re-flow a new part or was it a previously malfunctioning device? If it was the original device could you test with a new unit?

    Best Regards,

    Rick S.

  • We flowed a brand new part.
  • Hey Rick,

    Here are the screenshots of the switching node after the board was changed to have the switch node go directly to the inductor and bypass the vias. These are while VIO is at the 1V step before it goes high.

    1 = Switch node

    2 = LDO8

    3 = VIO output

    I noticed that the signals were a bit noisy and seemed to follow the switching node so I took one with the exact same setup without the switching node connected to see if it was just bleeding through on the O-Scope leads. THis is what they look like.

    Here is what they look like running normally. (Disregard the switching noise on the other signals.)

  • Hi Brian,

    This is interesting, the switch node looks like it inverts when LDO8 is active. If you disable LDO8, does it correct itself?

    If it doesn't, does disabling any other regulators change the behavior on VIO?

    Best Regards,

    Rick S.

  • Hey Rick,

    I have been trying to get a screen shot showing the rise of LDO 8 with the switching node but have been unsuccessful. I hope to get one today.

    We have tried turning LDO1-8, VDD1, VDD2, VIO and VDDCTRL off and back on to see what effect it has on VIO. THere was little to no effect. The only thing I saw was VIO go up in voltage by about 100mV when we would turn some voltages off. 

    I will continue to try and get a screenshot of LDO coming up and the switch node. 

  • I finally got a screenshot of when the switching node changes in reference to when LDO8 goes high.

    As you can see where I am zoomed in to show the switching node changing how it is switching is well before when LDO8 goes high.

  • Hey Richard,

    I am not sure why your last comment isn't here on the forum but I got it in my email. Here is a screenshot of the feedback from C129 which is as close as I can get to the Ball.

    Ch1 = Feedback on C129

    Ch2 = input of C126

    you can see that they follow each other exactly and there is nothing on the feedback until VIO starts up.