TPS65381-Q1: SPI_ERR injection

Hi Shimizu-san,

Please make sure you have downloaded the latest TPS65381A-Q1 datasheet, www.ti.com/.../tps65381a-q1.  Shortly after change management review the TPS65381-Q1 datasheet will be updated to Revision G with the same updates already in the TPS65381A-Q1 datasheet. The TPS65381-Q1 datasheet through Revision F did not have the SPI_ERR bits defined correctly.  These new revisions have many corrections and clarifications to make understanding for the device much simpler and more understandable.

A1:  The corrected SPI_ERR definitions are:

00b = No error

01b = SPI SDO error (mismatch on SDO output)

If both a SPI SDO error and another SPI error occur during the same SPI frame, 01b is shown in the SPI_ERR[1:0] bit

because the SPI SDO error has priority.

10b = Reserved

11b = SPI errors including truncated SPI frames, SPI transfers with more than 16 bits, SPI transfers with undefined commands or SPI transfers with incorrect command parity

With the corrected definition of the SPI_ERR bits the error received during the injection test matches what is expected. Directly related to this the definitions of STAT[2] and STAT[0] which provide SPI error information in the Device Status Flag Byte Response have also been updated for clarity to:

STAT[2] SPI SDO error (during previous SPI frame)

STAT[0] SPI errors including truncated SPI frames, SPI transfers with more than 16 bits, SPI transfers with undefined commands or SPI transfers with incorrect command parity (during previous SPI frame)

A2:  Same as A1, with corrected definitions a truncated SPI frame (ie 14 bits instead of 16 bits) is 11b in SPI_ERR.

Please let us know if you have further questions.

Best Regards,

Scott

Hi Shimizu-san,

The target for release of revision G to the web is by June 1, 2017.  It is in change management sign off process right now.

Best Regards,

Scott