TPS65217BEVM: Issue with Power Down Sequence

Jarret Adam

Part Number: TPS65217BEVM

We are using the TI’s AM3352BZCZ processor. So as recommended we are using the TPS65217B PMIC for providing the power rails. Our system is not a portable one so the battery is not used. Also we are not using any of the RTC or any power savings features so our PMIC gets enabled by directly pulling up the PWR_EN pin (pin 9); also we are powering the PMIC with an intermediate 5.1V rail (from the system 12 V input) using a DC/DC converter (using the TI’s TPS62140).

We are using the AC input to sense the power being available and start the PMIC.

Now….we noticed over time and after many Power ON-OFF cycles that the CPU failed regularly. Upon closer examination we found the VDD_CORE (and /or VDD_MPU) and 1.8V DDR are shorted to VSS on the CPU pins. Replacing the CPU fixes the dead boards…

Long story short I traced the failures on wrong Power-OFF sequence provided by the PMIC….

Our system are subjected to power input connector being disconnected at any time without sw shutting down the CPU in controlled manner….

As I mentioned the abnormal POFF sequence happens very rarely (less than 1 in 80 or so power plug disconnect…) but I was able to capture the event on the scope. Please see “cpu_poff_b1”and cpu_poff_b2” compared with the normal power off “cpu_poff”. I have to mention that the cpu on the board I used for getting the scopes had failed by the end of the testing day with the same failure: VDD_CORE and 1.8V DDR shorted to the VSS on the cpu pins….

As you can see the voltage on 1.8V DDR rail spiked to 3.76V (!!!!!!) briefly and the 1.1V VDD_CORE spiked to around 2.8V (!!!!!!)

Note:

green trace: VDD_CORE (DCDC3);

yellow trace: 1.8V rail (DDR rail and other) (DCDC1);

pink trace: 3.3V rail (VLOD3 – pin 40)

Going further I traced the problem to the fact that when the Voltage input to the PMIC DC/DC and LDO reaches the lower limit for the AC input (closed to 4.3V) nasty poff sequence and values can be seen (as seen in the above mentioned scopes captures.

Going further with investigations I start looking at the EVM for the TPS65217B (TPS65217BEVM). So after playing with the EVM for a while I could notice strange behavior on the EVM:

For example when using the AC or the USB input power connector (J3/AC or J3/USB input) the poff sequence will be correct executed (aside of sw power off) only in the case when the PWR_EN pin (JP9 pin 2) is pulled LOW. In all the other cases (input disconnected, and PB_IN, nRESET switches being actuated) the poff sequence is wrong and possible dangerous to a potential CPU connected to them…

The only way the poff sequence is executed correctly (in all conditions: disconnect, PB_IN, nRESET) is in the case of the BAT input being used.

Note:

I was able to fix the issue we had by using an external voltage supervisor following the 12V voltage input to pull-down the PWR_EN pin on the PMIC to correctly execute the poff sequence in the case when the power input plug was removed. (RESET pin does not work when the PMIC is using AC or USB input.)

Please see the attached scope captures as they are quite self-explanatory…..

Note:

“ac_evm_poff_disc” – 5.0V connected to the AC input (J3/AC) , power-off sequence disconnecting the 5.0V;

“ac_evm_poff_pbin” – 5.0V connected to the AC input (J3/AC) , power-off sequence pushing the PB_IN switch;

“ac_evm_poff_res” – 5.0V connected to the AC input (J3/AC) , power-off sequence pushing the nRESET switch;

“ac_evm_poff_en” – 5.0V connected to the AC input (J3/AC) , power-off sequence by disconnecting the JP9 jumper and connecting the JP9 pin 2 (PWR_EN) to JP9 pin 3 (PGND)

“bat_evm_poff_disc” – 5.0V connected to the BAT input (J2/BAT) , power-off sequence disconnecting the 5.0V;

“bat_evm_poff_pbin” – 5.0V connected to the BAT input (J2/BAT), power-off sequence pushing the PB_IN switch;

“bat_evm_poff_res” – 5.0V connected to the BAT input (J2/BAT), power-off sequence pushing the nRESET switch;

“bat_evm_poff_en” – 5.0V connected to the BAT input (J2/BAT), power-off sequence by disconnecting the JP9 jumper and connecting the JP9 pin 2 (PWR_EN) to JP9 pin 3 (PGND)

As I mentioned the USB input behaves exactly the same as AC input with some exceptions when the DCDC2 shows some artifacts when shutting down (removing the 5.0V input) please see “usb_evm_poff_disc2”. The ripples on the DCDC2 (1.1V) can be as high as 1.45V.

over 6 years ago

0 Jarret Adam over 6 years ago

Prodigy 75 points

0 Nastasha over 6 years ago

TI__Genius 10000 points

Jarret,

Thank you for reaching out with E2E. I have assigned this question to our application expert on this device. We will look into this and get back to you shortly.

Thanks,
Nastasha

0 Brian Berner over 6 years ago in reply to Jarret Adam

TI__Mastermind 30260 points

Jarret,

I'm sorry, but you will need to attach the images using the e2e "Insert Media" option in the text editor. DropBox is blocked on the TI network for file sharing and I cannot access the images.

It may only be necessary to attach a few of these images to see the problem, so you do not need to attach all 15 in your first reply.

0 Brian Berner over 6 years ago

TI__Mastermind 30260 points

Unfortunately, even when I see the images, it may only confirm what we already know: there is no battery in the system, so it appears that when AC/USB is abruptly removed the power-down sequence cannot execute properly.

The only workaround to avoid this would be to add a lot of bulk capacitance on the SYS pin (>100uF) or use a small battery connected at the BAT pin. This would allow extra current to be provided to the downstream power rails while they sequence down.

Additional capacitance could also be added between the TPS62140 and the TPS65217 in either scenario to help hold up the AC voltage, but the UVLO on this pin will lock it out under UVLO+200mV and then the system will need to rely on SYS again.

0 Catalin Palade over 6 years ago in reply to Brian Berner

Prodigy 180 points

Hi Brian,

I'm the said customer who experienced this issues with the TPS65217B and with the TPS65217BEVM.
Apart of your valid comments regarding the behavior when the power source is abruptly removed regardless of the input paths used (AC, USB or BAT), can you please comment the EVM with the 5.0V connected to the AC input case where attempting to power-off using the PB_IN will produce the power-off sequence as seen in the "ac_evm_poff_pbin" scope trace. (the 5.0V source was never removed from the AC input). Personally I was expecting the same power-off sequence as in the case where the EVM is powered using 5.0V source connected to the BAT input seen in “bat_evm_poff_pbin”.

Thank you.

0 Brian Berner over 6 years ago in reply to Catalin Palade

TI__Mastermind 30260 points

Catalin,

I have never been able to see these images. They cannot be on a server in a cloud sharing tool like Dropbox, unfortunately.

Can you please attach the images you are referring to inside the text editor embedded in e2e, using the icon that looks like a Polaroid photo, named "Insert/Edit Media" or put the images in a PDF and attached the PDF?

I think I will understand the problem better when I can see it :-)

0 Catalin Palade over 6 years ago in reply to Brian Berner

Prodigy 180 points

evm.pdf

0 Catalin Palade over 6 years ago in reply to Catalin Palade

Prodigy 180 points

Hi Brian,

Thanks for replying.

Please see attached the scopes in pdf file.

0 Brian Berner over 6 years ago in reply to Catalin Palade

TI__Mastermind 30260 points

Catalin,

Can you please confirm which Channels on the scope correspond to which pins on the TPS65217 device, specifically Channel 2 (Blue)?

I see:

"green trace: VDD_CORE (DCDC3);

yellow trace: 1.8V rail (DDR rail and other) (DCDC1);

pink trace: 3.3V rail (VLOD3 – pin 40)"

in the original post, but no mention of the color Blue. And are the other 3 channels consistently probing the same pin in every scope shot?

What I find strange is that in every image except the rare and very-rare "PMIC Abnormal Power-Off" sequences, Channel 2 shows a vertical scale of 4V/div. This means one of the voltages captured is >12V and is slowly ramping down.

It seems to me that in this rare case, the PGOOD signal from the 12V->5V supply would go low before the PMIC encounters a Fault. My advice here would be to AND this PGOOD with PMIC_PWR_ENABLE signal so that if either one goes low, the PMIC will power-down correctly.

In order for me to comment on your most recent question, I would need to see some additional signals captured on the scope.

I would suggest leaving only 1 DC-DC or LDO rail that powers-down too quickly (Ch2 or Ch4) and capture AC, PB_IN/nRESET, and BAT at the same time.

I need to see what the inputs are in order to tell you why the outputs are acting strange.

Thanks,

Brian

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TPS65217BEVM: Issue with Power Down Sequence