LP87524B-Q1: How fast ENx can be asserted after NRST?

Masatoshi Oguri

Part Number: LP87524B-Q1

Hello,

How fast ENx can be asserted after NRST?

I wonder if I have to wait for some moment to toggle ENx, because there must be some start-up process for the IC to come up. This is clearly explained for I2C in p.17 of the datasheet.

Is there some delay necessary like that for I2C? Or, may I assert NRST and ENx simultaneously, or tie them together?

Thanks.

Regards,

Oguri

over 6 years ago

0 Richard Solarski over 6 years ago

TI__Genius 10885 points

Oguri-san,

ENx appears to be level sensitive, not edge sensitive, so I do not see why they would need a delay. This leads me to believe they can be tied to NRST, but I'm looping in the product expert to verify.

Best Regards,
Rick S.

0 Masatoshi Oguri over 6 years ago in reply to Richard Solarski

TI__Expert 4780 points

Hi Rick,

Thanks!
The concern is that ENx hi before the completion of OTP reading might cause something wrong.

Oguri

0 Tomi Koskela over 6 years ago in reply to Masatoshi Oguri

TI__Genius 11020 points

Hi Oguri-san,

When NRST is set to high level (or shorted to VANA) this initiates power-on-reset (POR), OTP reading and

enables the system I/O interface. This startup sequence takes about 1.2ms. EN signals can be connected to NRST, but note that the startup delays will have additional 1.2ms delay due to internal startup sequence. Alternatively NRST could be connected to VANA to activate the internal logic and EN signals to start the buck converters.

Best regards,

Tomi Koskela

Power management

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LP87524B-Q1: How fast ENx can be asserted after NRST?