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TPS65381A-Q1: Why only NMASK_VDD1_UV_OV bit of DEV_CFG1 register used to mask VDD1 line ?

user5102395
Intellectual 320 points
Part Number: TPS65381A-Q1

Default,  when VDD1 UV(Under Voltage) / OV (Over Voltage) happens,   VMON of  TPS65381A-Q1 will detect this condition , but will not let ENDRV going to LOW status, because  NMASK_VDD1_UV_OV bit is set with 0 by default.  and there are no other register's bit  used to mask VDD3/5  or VDD5 line for OV / UV condition.  Why?

Is there the case,  VDD1 will not be used?  

VDD1 UV/OV  condition  is not worth for TPS65381A-Q1 to detected and let ENDRV to LOW by default?

 

  • 0
    TI__Mastermind 20580 points

    Hello,

    The TPS65381A-Q1 was developed to support a wide range of functional safety processors.  There are many use cases where the MCU requires only one voltage rail for both the core and IO supply, normally supplied by VDD3/5 from the TPS65381A-Q1.  In such cases VDD1 LDO controller will not be used and thus would be detected as a UV condition so the NMASK_VDD1_UV_OV bit is used to configure the TPS65381A-Q1 while it and the system are in DIAGNOSTIC state to cover any systems that are using this rail so that the TPS65381A-Q1 will then react to a detected UV or OV as outlined in the Device controller state diagram and internal signals.

    As quoted from Section 5.3.4 VDD1 Linear Regulator section of the datasheet:

    If the VDD1 regulator is not used, leave the VDD1_G and VDD1_SENSE pins open. An internal pullup device on the VDD1_SENSE pin detects the open connection and pulls up the VDD1_SENSE pin. This forces the regulation loop to bring the VDD1_G output down. This mechanism also masks the VDD1_OVflag in VMON_STAT_2 register and therefore the ENDRV pin action from a VDD1 overvoltage (OV) condition is also masked. These actions are equivalent to clearing the NMASK_VDD1_UV_OV bit in the DEV_CFG1 register to 0. This internal pullup device on the VDD1_SENSE pin also prevents a real VDD1 overvoltage on the MCU core supply in case of an open connection to the VDD1_SENSE pin, as it brings the VDD1_G pin down. Therefore, in this situation, the VDD1 output voltage is 0 V.

    By default, VDD1 monitoring is disabled. If the VDD1 pin is used in the application, TI recommends to set the NMASK_VDD1_UV_OV bit in the DEV_CFG1 register to 1 when the device is in the DIAGNOSTIC state. This setting enables driving and extending the reset to the external MCU when a VDD1 undervoltage event is detected.

     

    Best Regards,

    Scott

  • 0 in reply to Scott Monroe
    Intellectual 320 points

    Scott:

     thanks for your kind reply.

    It is the answer I wanted.

    Best Regards

    Dai mb