• TI thinks resolved

TPS65217: VLDO4 is 1V at shutdown with and without battery . How to bring it down to logic low ?

Part Number: TPS65217

I am using TPS65217C available in Beaglebone Black (schematics https://raw.githubusercontent.com/CircuitCo/BeagleBone-Black/rev_b/BBB_SCH.pdf for testing a protoype. I have tested it with and without battery. The BeagleBone Black is running the latest debian image from  elinux.org  https://elinux.org/Beagleboard:BeagleBoneBlack_Debian#Flasher:_.28lxqt-4gb.29_.28All_BeagleBone_Variants_with_a_4GB_eMMC.29. 

on issuing "systemctl poweroff" command from linux. I observe that the LDO4 voltage does not go down. Also observed that Vsys is dropping down to 3.94V from 5.5V ( I am using 4V battery)

I can clearly see PMIC PWR_EN bit go low. From I2C messages at boot up it is also noticed that the Status register is set to start the power down sequence when PWR_EN bit goes low.

My questions are

  1. Why does Vsys stay high ? 
  2. What is preventing the PMIC from shutting down ?

AA

  • Hi,

    I have assigned your request to concerned Applications Engineer and we will get back to you as soon as possible. Please note that this is vacation time in US and there may be some delay in answering your question.

    Regards,

    Murthy
  • Hi Ajeya,

    Our primary application support for this device is out of office for the holidays so please allow for some delay. Thank you for searching E2E first, I saw your post on a similar issue and appreciate your efforts. I will try to provide some guidance in the meantime.

    For the VSYS, what I2C commands does "systemctl poweroff" send to the PMIC? That may help explain why the power path switches VSYS from USB / AC to Battery power (for example, if USB_EN bit is set low). Are the AC / USB pins still powered after the command? What voltage are they at?

    On the other post, you mention that LDO4 is dropping down to 1V which would suggest that the LDO itself isn't regulating anymore. Brian had suggested maybe this rail is actually being pulled up by leakage through a different IC. There are a couple tests you can run. The first would be to add a small pull down resistor to LDO4 and see how the output voltage changes. If there is a pull-up through an external chip to VSYS then you could calculate that resistance based on the voltage change. Alternatively, you could cut the trace connecting the LDO4 output from the PMIC to the rest of the board to see if the voltage is on the PMIC side or the board size, but that would be a bit destructive. Do you have any scope shots of the LDO4 behavior?

    Thanks,

    Kevin LaRosa

  • In reply to Kevin LaRosa:

    [Moderator Edit: removed I2C commands as it was causing lag when viewing this post and doesn't appear to be the related to the issue]

    Please see the end of the above for I2C traffic. THe above is complete I2C traffic from start to shutdown(systemctl poweroff command).

    The above shot is from Logic analyser showing Vsys going down to 3.7V . The BBB has both battery and 5V adpater connected

    . Here LDO4 corresponds to V3.3B above shot

    AA

  • Ajeya Anand
    Why does Vsys stay high ?

    When in shutdown state, Vsys is tied directly to Vbat. What you're observing is normal behaviour.

    Ajeya Anand
    What is preventing the PMIC from shutting down ?

    Nothing. The reason you're seeing vdd_3v3a (normally fed by LDO4) remaining high is not due to the PMIC but due to external current being injected into I/O of the AM335x, which is funneled back to vdd_3v3a via the internal protection diodes of the I/O cells. Needless to say, this situation is not healthy for the processor and should definitely be avoided.

    The origin of this current is various components (mostly pull-ups) powered by vdd_3v3b, which is provided by a separate LDO (not part of the PMIC) which is undesirably remaining active in your scenario. See this post and follow-ups for a discussion of this problem.

    The simplest workaround is removing this LDO (U4) and replacing it by a hard interconnection between vdd_3v3a and 3v3b, like this.

    Matthijs van Duin — Dutch & Dutch

  • In reply to Matthijs van Duin:

    Hi Matthijs,

    Thank you for stepping in providing guidance on these issues, especially during the holidays.

    One item I'll add for Ajeya is that the VSYS behavior is described in the datasheet section "Device Functional Modes" starting on page 38, with a nice flow chart on page 39 which notes that when the power path is off, VSYS is connected to VBAT as noted by Matthijs.

    Thanks,

    Kevin LaRosa

  • In reply to Kevin LaRosa:

    Does it help 

    If just before shutdown I disable the MUX using  MUXCTRL register = 0x00 ?

    I wish to have  a total shutdown and Vsys should not be supplied by battery at that point.

    AA

  • In reply to Matthijs van Duin:

    Thank you Matthijs. I need to use a regulator there to drive higher load. PMIC LDO4 supplies max of 400 mA and the requirement is 1A. Is there another way to overcome this issue ?

    AA

  • In reply to Ajeya Anand:

    Ajeya Anand
    Does it help if just before shutdown I disable the MUX using  MUXCTRL register = 0x00 ?

    I wish to have  a total shutdown and Vsys should not be supplied by battery at that point.

    The analog mux is not relevant here. There is no way to prevent Vsys to be connected to the battery in shutdown state, this is hardwired behaviour.

    Ajeya Anand
    Thank you Matthijs. I need to use a regulator there to drive higher load. PMIC LDO4 supplies max of 400 mA and the requirement is 1A. Is there another way to overcome this issue ?

    You could use an external regulator, but you'd need to be very careful with signals crossing between the two power domains (I/O of the AM335x powered by VDD_3V3A/LDO4 and your external hardware). You could use a level shifter for example, or isolate the connections using a bus switch enabled by the reset signal.

    Since no such care has been taken between the AM335x I/O and various hardware on the BBB powered by VDD_3V3B, regulator U4 should still be replaced by a hard connection.

    Matthijs van Duin — Dutch & Dutch