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TPS65094: bootstrap capacitor TPS65094 PMIC placement

Part Number: TPS65094

Hello. I read design guide for TPS65094 PMIC.

In SLVUAK0.pdf? page 14  i read requirement  - "  The bootstrap capacitor should be placed close to the IC rather than near the FET,

though other components, such as the input capacitors, will take a higher priority."

But, in evalution board design, this apacitor placed close to FET pin? and  through 0 om resistor to controller pin.

I can not use zero resistors? and place a capacitor between  SWx and  BOOT pins close too controller?  Capacitor can be placed in bottob layer?

  • Hi Eugene,

    Thank you for reading the design guide and hopefully I can make it more clear.

    For the EVM, the FETs are also close (within an inch of the PMIC), so close to the PMIC and close to the FETs in this case is the same thing. If the FETs are located far from the PMIC (say 4 inches), then I would recommend placing the bootstrap closer to the PMIC rather than closer to the FET.

    The 0 ohm resistors are included to allow for optimization of the controller loop. There are several good articles that discuss controller loop optimization, I've linked to a couple at the bottom here. You don't necessarily need DRVH 0 ohm, BOOT 0 ohm, and DRVL 0 ohm. Generally the DRVL EMI is a lot less (difference between GND and Vout is a lot less than VIN and Vout for most cases) so DRVL 0 ohm can be omitted. Additionally, BOOT 0 ohm and DRVH 0 ohm effectively perform the same role so generally only one is really needed. You can place the boot cap on the bottom layer.

    Let me know if you have further questions.

    www.ti.com/.../slyt465.pdf
    www.ti.com/.../slpa010.pdf
    e2e.ti.com/.../how-to-use-slew-rate-for-emi-control
  • Kevin, Thank you for your reply.
    Now I can optimize my design.