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TPS65023: Start up issue with an AM3505

TISL
Expert 3795 points
Part Number: TPS65023
Other Parts Discussed in Thread: AM3505, TPS650250

Dear E2E Support,

My cutomer has some start-up issue with our TPS65023 which power our AM3505.

Here is his description below:

On scope 5 :

-          Yellow trace => +5V_ALIM (Main Power supply of the PMIC)

-          red Trace => +1.8V (Power supply of DDR and a part of the CPU)

-          Green Trace => +3.3V (Power supply of main 3.3V)

-          Blue trace =>  VDDSHV_EN (Enable command of +3.3V PMIC Output)

Scope5

 

I do not understand what happened on +1.8V.

The start up is OK and 1.8V is reach for 2ms and it continue to rise until 2.7V. The slope seems the same as +5V_ALIM and +3.3V_ALIM.

 

Do you know this problem and how to solve it?

 

We have some products where the +1.8V stays always to 2.7V supply and the board is KO (it’s not possible to launch application…)

When we withdraw the CPU, after start up, Power supply 1.8V is OK. It doesn’t rise until 2.7V.

 

First remark : When I put a 100nF capacitor on VDDSHV_EN (or for C70 ), power startup is OK (see scope 4). But we must be carefull because the +1.2V(for the core supply) and 1.8V_USB/3.3V_USB LDOs will start before the 3.3V (is it a pb?)

Scope4:

Second remark  : 3.3V – 2.7V = 0.6V it seems to be a voltage clamp diode ! What is the electronic interface between the +1.8V domain (VDDS/VDDS_SRAM/VDDS_DPLL/VDDSOSC) and +3.3V domain (VDDSHV) of the CPU?

Other scope if it can help to understand the power supply sequence:

Scope_8

Yellow: +5V_ALIM

Green: +3.3V

Pink: +1.8V

Bleue: +1.2V

And scope_9:

Yellow: +5V_ALIM

Green: +3.3V_USB

Pink: +1.8V

Bleue: +1.8V_USB

I can share the schematic in private message if needed.

Regards,

  • 0
    TI__Genius 17380 points
    Hello,

    I have assigned this thread to the device expert. On first glance, it looks like the 1.8V rail is being pulled up by the load as you mentioned (diode drop). Given that delaying start-up of the 3.3V rail with a capacitor seems to fix it, this could be related to power up sequence timing. Can you delay powering up any of the rails until the 5V has reached 5V?
  • 0
    TI__Mastermind 30260 points

    The TPS65023 should follow the proper sequencing requirements for the Sitara processor.

    As you and Kevin already mentioned, the voltage of 3.3V - 2.7V = 0.6V is a diode drop and the I/Os of the Sitara processors are not fail-safe. The 3.3V rail should wait a couple milliseconds (~2ms) after the 1.8V rail is  powered on. The delay in your first scope shot (#5) should be used as a guideline for the length of the RC delay.

    Although I do not know all of the distinctions between the AM335x and AM3505 processors, the TPS65023 would be sequenced the same way as the TPS650250 when using the EN pins only. This User's Guide should be helpful in providing the correct method for sequencing the PMIC using external analog components (diodes and R-C circuits for delay).

  • 0 in reply to Brian Berner
    Prodigy 30 points

    Hi all and thank you for your answer !

    I managed to delay the rise of the 3.3V (C70 = 56nF et C69 = 100nF) in order to wait the end of 5V rising.

    Note that we cannot delay the +1.8V because it enable pin is directly connected to the +5V_ALIM.

    it  does not solve the problem.

    If you have the schematic, you will see that we use a supercapacitor and a 3V battery.

    It is necessary to maintain the SRAM power supply and RTC chip.

    When the battery is present or supercapacitor charged (and 3.3V is delayed) , at start-up, we never see the problem of 2.7V on 1.8V output.

    Blue => +3.3V

    Red => +1.8V

    Yellow => +5V_Alim

    Green => +3.3V_USB (LDO output)

  • 0 in reply to olivier Barbedette
    TI__Mastermind 30260 points

    I will need schematic to debug this issue further. Please do not send schematic in Private Message on e2e. The private messaging system is not built to support offline debug.

    If you cannot attach schematic in public forum, you can share by e-mail and we will post issue resolution on e2e to Close the question.

  • 0 in reply to Brian Berner
    Prodigy 30 points

    Complementary measures have been done for 4 boards  :
    All the start up are OK when :

    - +3.3V and +1.2V are delayed

    -  The battery is present 

    Essai_2v6pour1v8.pdf

    So if the supercapacitor C156 is not present, the behavior is satisfactory.

    It seems that the current draw due to the supercapacitor(if discharged) is the aggravating factor which cause this overvoltage.

     

  • 0 in reply to olivier Barbedette
    TI__Mastermind 30260 points
    Olivier,

    Thank you for confirmation.
  • 0 in reply to Brian Berner
    Prodigy 30 points

    Hi Brain,

    Yes, you are right. When supercapacitor is present, the default appears when it is discharged.

    We need to keep this supercapacitor in order to maintain power supply on SRAM and RTC during changement of the battery (every 10 years !).

    Now, i wanted to know where is the preferred path of the current during the chargement of the supercapacitor.