TPS65381A-Q1: Register status after fault condition is cleared

Yuta Kurimoto,


For the VDD5 regulator, the overtemperature condition clears the VDD5_EN enable bit and transitions to the RESET state. NRES pin goes low and resets the MCU and the ENDRV pin is low. All other regulators remain enabled. When the VDD5 overtemperature condition is gone, the MCU must set the enable control bit again to re-enable the regulator.

VDD5_ILIM: VDD5 current-limit status bit
– Set to 1 when a VDD5 current-limit condition is exceeded
– Cleared to 0 if a current-limit condition is no longer present
Note: This status bit is valid only when the VDD5_EN bit in SENS_CTRL register is set to 1. When the VDD5_EN bit is
cleared to 0, this bit will be 1.

VDD5_OV: VDD5 overvoltage status bit
– Set to 1 when a VDD5 overvoltage condition is detected
– Cleared to 0 if an overvoltage condition is no longer present
Note: This status bit is valid only when the VDD5_EN bit in SENS_CTRL register is set to 1. When the VDD5_EN bit is
cleared to 0, this bit will be 1

Only the overtemperature will clear the enable bit. all other conditions will clear when the problem is no longer present.

Hello Gordon,

I think there is misunderstanding so let me explain more detail.

In the TPS653850-Q1 datasheet, it says
"The TPS653850-Q1 device also has an error reporting capability through the SPI register. The device has
separate status bits in the SPI register for each specific error on the system level or device level. When
the device detects a particular error condition, it sets the appropriate status bit and keeps this status bit
set until the MCU reads-out the SPI register in which this status bit was set. Based on which status bit
was set, the MCU can decide whether it must keep the system in a safe state or whether it can resume
with the operation of the system"

I think this sentence means that "even though the error condition is removed, the corresponding SPI status register is latched high until MCU reads the register."
For example, VDD5 detects OV and then VDD5_OV register sets to "1". When OV condition is gone, but VDD5_OV register still "1". Only after MCU read the VDD5_OV register, the register become to "0".
I think TPS653850-Q1 has such a latch function.

Does TPS65381A-Q1 has same function?

Let me know if you have any question.
Thanks,
Yuta Kurimoto

Hello Gordon,

Could you please support above question?

If my explanation is unclear, please let me know. I will make more clarification.

Customer need to decide part within this month, so I need the answer asap.

Thanks,

Yuta Kurimoto

Hi Kurimoto-san,
My apologies, I was not aware of a latching register in the TPS65381A-Q1. I went to ask the System Engineer for this part to verify.

His comment:
We do have error flags on SPI in TPS65381 and I guess they will be latched before sending it on SPI. But I am not aware of any “clear after MCU read” bits like TPS653850-Q1. (or like the latch you mentioned) .
ABIST_ERR flag is latched as long as successful ABST run is completed. VU/OV error flags are set as long as error is present.. etc..

Let me know if you need more information. I will go back to the Systems Engineer for this part.