TPS65094: TPS650942 RSMRSTB auto reset

Hi Keny,

Table 6-2 in the datasheet defines the signals that affect RSMRSTB, do any of these have correlations with the de-assertion?

Best Regards,
Rick S.

Keny,

RSMRSTB should be asserted when BUCK1, 4, 5, PMICEN and THERMTRIPB are all high, as per table 6-2 in the datasheet. I would check these during this low period.

As for the delay between SLP_S3B and VTT I would check the state of the SLP_S4B and PCH_PWROK pins as well.

Thank you,
Nick

Dear Sir

Other signals are as below.

But I think the RSMRST is eariler than other signal drop.

Please check these picture.

Thanks.

Keny,

Based on these screenshots it looks like the PMIC is shutting down.

If you can read the PWR_FAULT_STATUS1, PWR_FAULT_STATUS2, and OFFONSRC registers on the device those will tell you the source of the shutdown.

I am thinking it will probably a BUCK5 powerfault due to that upwards spike.

Also if you want to send me your layout I can take a look at it and see if there is anything that doesn't look right.

Thank you,
Nick

Hi NIck

Thanks your reply.

How can we read these register?

BIOS can read these register by I2C?

If power on success once, these register can be kept or be cleared?

I will measure the switching node of buck5.

Thanks a lot.

Keny,

Do you have any updates on this?

Thank you,
Nick

Hi Nick

It seems the layout need to be modified.
Thansk.