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TPS65217CEVM: Support for validating the PMIC EVM

Harshavardhan Kalavakunta
Prodigy 160 points
Part Number: TPS65217CEVM
Other Parts Discussed in Thread: TPS65217

HI,

This is Harshavardhan and we have ordered a PMIC EVM (TPS65217C).

We are trying to validate the PMIC.

Do we have any provision of giving the separate input (apart of AC or battery) to the DCDC converters in the PMIC. 

When we wanted to go for the line transient of DCDC converters in this PMIC, we are supposed to give the input separately to the DCDC converter.

If we have any alternate method of doing the line transient of DCDC in this PMIC please let us know about it.

The quiescent current measurement is possible for individual DCDC's and LDO's.

How can we do RDS ON measurement in this PMIC for individual DCDC's.

Can you suggest us what all we can validate in the battery charge path.

Thank you in advance,

Harsha

 

  • 0
    TI__Genius 17380 points
    Hi Harshavardhan,

    Unfortunately the TPS65217CEVM does not have a way to separate the individual regulator inputs from the general SYS net.

    For doing a line transient, what I generally do for cases where the input supply cannot be easily separated from the input pin is to just connect a transient load in parallel with my regulator being tested. My load transient board is a resistor + FET where the resistor sets the current target and the transistor allows me to turn the load on and off.

    For quiescent current, I would recommend taking a measurement with the buck disabled and then again with the buck enabled when powering from the BAT node (VSYS = VBAT) and subtracting the difference.

    RDSON cannot be easily measured for any of our buck converters, it is tested during production, not as a stand-alone test. An estimate could be to draw a heavy load and measure the voltage difference between the input pin voltage and the switch node voltage and dividing by the current load. The low side FET could be done similarly with the GND pin. Note that these will include the parasitic resistances of bond wires and routing.

    For the battery charger / power path, you could validate the various settings like Voreg, Iprechrg, Iterm, etc based on Figure 13 in the datasheet.
  • 0 in reply to Kevin LaRosa
    Prodigy 160 points

    Hi 

    Thank you for the support.

    As we are working on validating the EVM TPS65217CEVM.

    We tried to load the DCDC converter in the PMIC. For the low currents(Up to 50mA) the output is fine.

    when we go for the higher load currents the input voltage is getting dropped pulling down the sys voltage.

    The input supply has a limit of 2A .

    So, please do support us in solving problem in loading the DCDC for higher value of load current.

    The supply of 5V is given to the AC.

    Thank you in advance.

    Regards, 

    Harshavardhan. 

     

  • 0 in reply to Harshavardhan Kalavakunta
    TI__Mastermind 30260 points

    Please provide a scope shot showing the voltage at the pins you refer to: AC, SYS, and DCDCx.

    It would also be helpful to see the current going out of the SYS pin, if possible.

    A schematic of your design would also be helpful.

  • 0 in reply to Brian Berner
    Prodigy 160 points

    Hi 

    Thank you for the support.

    The problem was with source meter we got that. Now we are able to load the modules.

    So, i have a question for you.

    If their is no separate input pins to the modules (DCDCx and LDO) the line regulation that we can check is from 4.3 to 5.8 using the AC pin for the converters.

    If that is a case we are supposed to go only with the range mentioned in the inputs [ ie., AC(4.3 to 5.8V ) or BATTERY(2.75 to 5.5V )] for line regulation test.

    Do we have any other method to do line regulation for each module? 

    Thank you in advance.

    Regards,

    Harshavardhan.

  • 0 in reply to Harshavardhan Kalavakunta
    TI__Mastermind 30260 points
    Harshavardhan Kalavakunta,

    You are correct. The only way to supply power to the DCDCx and LDOx regulators is by applying power at the main input pins of the PMIC (AC, USB, or BAT).

    Unfortunately, on the TPS65217CEVM, there is no way to disconnect the VIN_DCDCx pins or VIN_LDO pin from the SYS net.

    AC will operate correctly from 4.3-5.8V, but BAT will not operate below the UVLO value. The default UVLO value is 3.3V for all TPS65217 variants (A, B, C, D), and the default max charging voltage is 4.2V. Since you cannot change the EEPROM of the PMIC, BAT should only be tested from 3.3V to 4.2V
  • 0 in reply to Brian Berner
    Prodigy 160 points

    Hi,

    Thank you for the support.

    We are going with the input ranges for taking line regulation.

    Yesterday we tried in taking the power up/down sequencing.

    Everything is as expected but when the INSTDWN bit high, all the rails are supposed to shutdown at once but it is not happening.

    If we wanted to use INSTDWN, do we have anything to set or check with? 

    Thank you in advance,

    Ragards,

    Harshavardhan K 

  • 0 in reply to Harshavardhan Kalavakunta
    TI__Mastermind 30260 points
    Harshavardhan K ,

    Indeed, the INSTDWN bit only has an effect when "when the power-down sequence is triggered." There are two things you need to consider when using the INSTDWN bit.

    1) The other events that will trigger the power-down sequence are listed as bullet points in Section 8.3.1.2 Power-Down Sequencing on page 21 of the datasheet:
    • The SEQDWN bit is set.
    • The PWR_EN pin is pulled low.
    • The push-button is pressed for more than 8 s.
    • The nRESET pin is pulled low.
    • A fault occurs in the device (either an OTS, UVLO, or PGOOD failure).
    • The PWR_EN pin is not asserted (pulled high) within 5 s of a power-up event and the OFF bit is set to 1b.

    2) There is a minimum on-time of 5 seconds, shown in Figure 24. Global State Diagram on page 39 of the datasheet, which impacts the normal sequence-down events (setting SEQDWN bit and pulling PWR_EN pin low). If one of these power-down sequence events is used, the PMIC will not shut off until the 5s timer has expired. Using the nRESET pin and faults override the minimum on-time, but these are shown as the RED bubbles in the Global State Diagram to indicate they are special transitional states.