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TI Home » TI E2E Community » Support Forums » Power Management » PMU » TPS659xx PMU Forum » Warm reset out pulsing after power up
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Warm reset out pulsing after power up

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Rahul16136
Posted by Rahul16136
on Jan 12 2010 11:02 AM
Intellectual300 points

Hi,

     I am using TPS65930 PMIC chip for OMAP3530 processor. After power up -

1. PMIC voltages ie., VMMC1, VDAC & VAUX2 are showing 0V.

2. Warm reset out from processor is pulsing.

3. Also DDR clock from processor is pulsing according to the warm reset out signal ( ie., DDR clock is coming for some duration of time & repeatedly after every warm reset ).

Please let me know what might be the issue for the above points.

 

 

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  • Gandhar Dighe
    Posted by Gandhar Dighe
    on May 13 2010 17:29 PM
    Genius15110 points

    Hi Rahul,

    I am not sure why you are seeing this.

    Why do you have a switch on nRESPWRON? We generally recommend that you connect nRESPWRON from PMIC directly to SYS_nRESPWRON on OMAP. If you want to reset OMAP you can do that from I2C, power supplies will stay ON and OMAP will undergo a reset. I think this should be possibe.

    If you are using SW2 to reset OMAP then I would guess that SYS_nRESWARM on OMAP is configured as an input. Do you also reset the PMIC with SW2?

    For this also we recommend you connect OMAP and PMIC together and control reset from OMAP.

    What is the reason for external rests, I am not able to understand your reset circuitry. Is it possible to create a block diagram or a simple explanation of the circuit.

     

    Regards,

    Gandhar.

     

    Regards,
    Gandhar

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  • Rahul16136
    Posted by Rahul16136
    on May 19 2010 11:33 AM
    Intellectual300 points

    Hi Gandhar,

                          The external reset issue is solved. There was some issue with one of the boot pins (floating). But I was not able to understand the problem because the processor was booting properly & external reset was getting affected.

    External reset is an optional reset, which is ORed with the reset coming from PMIC (nRESPWRON) & then given to SYS_nRESPWRON of the processor.

    Still I am facing some other issues:

    1. When SW2 (SYS_nRESWARM) is asserted, the processor gets reset  exactly after 10seconds.

    2. SYS_SECURE_INDICATOR & SYS_DRM_MSECURE pins are always driven high by processor. Even if I am configuring these pins as GPIOs & making it to go low, still there is no change in its state.


    Thanks & Regards,

    Rahul.

     

     

     


     

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  • Gandhar Dighe
    Posted by Gandhar Dighe
    on May 23 2010 22:11 PM
    Genius15110 points

    Hi Rahul,

    Glad to know you were abke to resolve the reset issue. For the 10 seconds reset can you provide some more information. Briefly explain your warmreset circuit, please metion the steps that happen for warmreset.

    I don't know why your are seeing a 10second delay. If your info is not sufficient, I may need to look at the schematics.

    For the second question - please ask OMAP support. I will not be able to help with that. I hope these symptoms are not related to each other.

     

    Regards,

    Gandhar.

     

     

    Regards,
    Gandhar

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