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TPS659xx PMU Forum
Connection problem about "PWRHOLD" pin of TPS65910 for AM3517 ?
I want to use TPS65910 for AM3517 power management, but I don't understand "PWRHOLD" should be connected to?
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Thanks for your answer, but I find TI's application report (TPS65910 User Guide For AM3517/AM3505 Processor), "PWRHOLD" is connected to VDD2 or VIO.
But in cranboard;s schematic, it connected to VRTC.
What difference from them? (because VIO, VDD2, VRTC has different time slot, ex: VRTC is always 1.8V)
Which is the better suggestion for " PWRHOLD" connection?
The whole idea is to set PWRHOLD to high within the specified time to keep the device in active state. This can be satisfied with VIO, VDD1, etc.
You can follow crane board and connect it to VRTC.
OK, I see. Thanks!
I will reserved 2 choices on my platform,
choice 1: (crane board sloution)
PWRHOLD connected to VRTC, and when power on TPS65910, it enter in active state immediately.
PWRHOLD connected to VIO/VDD1, and when power on TPS65910, it should be wait user to press switch-on button ( PWRON is "low" in several milli-seconds). and TPS65910, it enter in active state.
I would say stick to choice 1.
I didnt understand choice 2, how is PWRON connected on board?
Because I want to reserve a push-button to control TPS65910 power on/off, (crane board has no push-button to control TPS65910 power on/off),
So, I think if PWRHOLD connected to VIO/VDD1, TPS65910 needs user to press push-button to power on it.
Does this configuration workable?
Choice 2 description is a bit confusing.
You want to have a push-button on PWON pin, is that correct. This will allow you to power on the device by pressing the push-button. In this case it doesnt matter where PWRHOLD is connected.
Please explain if I have understood this wrong.
You are right, "PWRHOLD " and "PWRON" are conditions for TPS65910 active state alternatively, (TPS65910 datasheet page.41)
How long does the "PWRON" signal drive to low level to active the TPS65910? If I use push-botton, is it OK? (Because user may press the button quickly), or I should choose SPDT switch alike?
A push-button will suffice. A small pule works fine for powering up. We have such a push-button on our lab board and it works as expected.
OK, Thanks for supporting!
I do have problem with this PWRHOLD connection and really hope you can help to confirm it: as my understanding PWRHOLD is used to maintain Power ON status after all of power rails are up, and it should also return to zero once power -off procedure is completed. According to this it is make sense to connect this pin to VIO, but I don't understand how it could work if it connected to VRTC because VRTC is a "ALWAYS-ON" rail as long as VBAT is applied. It means PWRHOLD will never go chance back to zero unless the battery is removed. How it could be used for power control if it is done this way?
I also have problem to turn off TPS65910 even I have PWRHOLD connected to VIO(directly), simply because VIO was not fully back to zero after shunt-down process(for some unknown reason) so that PWRHOLD remain at a certain of level (about 0.8V), it causes TPS65910 back to power on status again.
Could you please help on this please? Thanks!
As you said, if PWRHOLD is connected to VRTC, PWRHOLD won’t go back to zero and consequently we cannot say that PWRHOLD is used for power control.
PWRHOLD pin is usually connected to an external signal for PMIC power up/down control. If we look at the "Device state control through PWRON" timing diagram (p32 of the TPS65910 datasheet), we can notice that there is a delay (called t_dONPWHOLD) to set high PWRHOLD signal or DEV_ON control bit after NRESPWRON is released to keep on the supply.
If you do not want to use this functionality, you can put PWRHOLD to a high level. To do it, the best way is to connect it to VRTC because it is part of its supply domain (see table exposing the terminal functions p38 of the TPS65910 datasheet).
Hope this helps,
Hello Flore Auzanneau,
t_dONPWHOLD - delay to set high PWRHOLD signal or DEV_ON control bit after NRESPWRON released to keep on the supplies.
What is the significance of the delay? if we make PWRHOLD signal high before that delay or before NRESPWRON goes to high, what will happen?
When we set DEV_OFF bit, PMIC will turn off. Is it necessary to make the PWRHOLD signal low to keep the device turn off?
If the above requirement is true to turn off the PMIC than how can PMIC_PWR_EN ( this signal will remain active till the RTC domain of AM335x is powered) signal of AM335x be used for PMIC PWRHOLD as implemented in AM335x EVM or it means AM335x EVM cannot be turn off by setting DEV_OFF.
t_dONPWHOLD allows the processor to acknowledge the power on sequence and complete it. Indeed, after receiving NRESPWRON, the processor can complete the power on sequence by setting PWRHOLD or the DEV_ON control bit to 1. The typical value of the delay is 984ms (see datasheet p33).
It is not necessary to make the PWRHOLD signal low to keep the device turn off. If DEV_OFF bit is set to 1, then the POWER ON will be disabled.
Hope it helps,
When we set the DEV_ON bit the device will turn off once but restart again as PWRHOLD is the enable condition of the device as per my understanding( pg-41).
Can we make PWRHOLD high before NRESPWRON goes high through some external device?
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