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TPS65910A3 PWRHOLD

Nikhil Tiwari
Intellectual 575 points
Other Parts Discussed in Thread: AM3352, TPS65910

Hi,

For TPS65910A3, the user guide document 'SWCU093C' has the power on timings for TPS65910A3 when connected to AM3352. It shows that pwrhold ramps up just after the VRTC supply is stable.

In our case we have connected the PWRHOLD input to an open drain reset. and a pull up is provided to VMMC supply of PMIC. In this case when the board is powered on (when VMMC is not present) because of internal pull down on PWRHOLD pin this signal will remain low.

In this case will the PMIC start normally? the PWRHOLD will only go high when VMMC is present.

Thanks & Regards,

Nikhil

 

  • 0
    TI__Expert 6090 points

    Nikhil,

    you need to make sure that as soon as PMIC boots up , you are wrtting to DEVON bit as soon as PMIC boots up within 1 sec of device startup other wise device will shudown. So there is an option to connect it to VRTC.

    connecting  VMMC to PWRHOLD is ok as PWRHOLD is only needed when PMIC isactive.

     

  • 0 in reply to Puneet Sehgal
    Intellectual 575 points

    Hi Puneet,

    In our case now we have connected PWRHOLD to system reset (active low) and provided a pull up to VMMC supply generated by the PMIC. Then this should work without writing the DEVON bit also.

    Thanks & Regards,

    Nikhil

  • 0 in reply to Nikhil Tiwari
    TI__Expert 6090 points

    Nikhil,

    if you pull PWRHOLD high after resetuout going high , this should be fine. You dont need DEVON in this case.

  • 0 in reply to Puneet Sehgal
    Intellectual 575 points

    Hi Puneet,

    One more doubt, As active low transition on PWRON starts the device. If we are leaving PWRON floating and tying the PWRHOLD to VAUX2 supply will it still work.

    Figure 4. in datasheet shows 'device Turn-On/Off with Rising/Falling Input Voltage' which shows that device can start without just after the input supplies are applied. I think this feature is activated only if VMBHI_IT_MSK bit is set to 0 that is decided by EEPROM configuration.

    In 'TPS65910Ax User's Guide For AM335x Processors' document (SWCU093C) the default value for this bit is set to 1. Does it means we can't change it and it will be remain fixed for boot mode 10?

    Regards,

    Nikhil

  • 0 in reply to Nikhil Tiwari
    TI__Expert 6090 points

    PWRHOLD pins when pullled high will wake up the device , this is correct.

    VMBHI_IT_MSK is set in the EEPROm it can not be changed on the fly once set it reamin like that for EEPROM boot mode.

  • 0 in reply to Puneet Sehgal
    Intellectual 575 points

    Hi Puneet,

    If we are tying PWRHOLD to VAUX2 supply. It can go high only after 1.8, 1.5 supplies are stable. In this case the timing diagram given in Figure 3 of document 'SWCU093C - TPS65910Ax User's Guide For AM335x' is not satisfied. Please let me know if the PMIC will still wake up?

    Thanks & Regards,

    Nikhil   

  • 0 in reply to Puneet Sehgal
    Guru 19835 points

    Hi Puneet,

    PWRHOLD can be connected to VRTC or VDDIO or VCC7.

    http://e2e.ti.com/support/power_management/pmu/f/43/t/160461.aspx

    VRTC power mode in OFF state is the Low power mode, and in ACTIVE state is the Full power mode.
    If a condition of POWER ON enabled and VCC7>VMBCH is met, an OFF-to-ACTIVE state transition is caused.
    PWRHOLD signal high level which is a condition of POWER ON enabled is more than 1.3V. VMBCH value (VMBCH_REG.VMBCH_SEL[1:0]) in EEPROM Configuration is 3V.
    Therefore, if PWRHOLD is connected to VRTC or VCC7, when VCC7 reached 3V, an OFF-to-ACTIVE state transition is caused.

    When VCC7 reached 3V, is VRTC power mode the Full power mode? If not so, how many is the delay to the Full power mode after VCC7 reached 3V?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Expert 6090 points

    Daisuke,

    VRTC is in full power mode or not will depend on the EEPROm bit. if the bit is set, then after VRTC turning on, it will be set to high power mode.

  • 0 in reply to Puneet Sehgal
    Guru 19835 points

    Hi Puneet,

    Thank you for your reply.

    Our customer uses TPS65910A3, not TPS65910A31. When VRTC is the Low power mode, it can not supply AM335x VDDS_RTC. In Figure 1 in User's Guide SWCU093C, VRTC is not connected to VDDS_RTC.

    When PWRHOLD is connected to VRTC or VCC7, can VRTC supply VDDS_RTC?

    Best regards,

    Daisuke

     

  • 0 in reply to Puneet Sehgal
    Guru 19835 points

    Hi Puneet,

    TPS65910 datasheet describes the PWRHOLD input as follows.

    "When none of the device power-on disable conditions are met, a rising edge of this signal causes an OFF-to-ACTIVE state transition of the device"

    "This input signal is level sensitive and no debouncing is applied."

    Is the PWRHOLD input the level sensitive or the edge sensitive?

    When PWRHOLD is connected to VRTC, is an OFF-to-ACTIVE state transition really caused?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Expert 6090 points

    Hello daisuke,

    When VRTC is in low power mode , it should not be connected to VRTC of processor.

    Best approach is to leave VRTC alone and do not connect any load to this just a 2.2uf cap..

     

    T

  • 0 in reply to Puneet Sehgal
    Guru 19835 points

    Hi Puneet,

    Thank you for your reply.

    TPS65910x Schematic Checklist (SWCA139B) describes PWRHOLD as follows.

     "If control is not required, then can be tied to VRTC"

    If control is not required, should PWRHOLD be connected to VCC7, not VRTC?

    TPS65910Ax does not automatically switch-on at NOSUPPLY-to-OFF or BACKUP-to-OFF transition since INT_MSK_REG.VMBHI_IT_MSK bit in EEPROM Configuration is 1.

    If PWRHOLD is connected to VCC7, is NOSUPPLY-to-OFF and OFF-to-ACTIVE state transition automatically caused?

    Is it certain that PWRHOLD input is level sensitive? If PWRHOLD input is edge sensitive, the transitions will not be automatically caused.

    Best regards,

    Daisuke