Q:

From datasheet I think /INT goes Low at following condition.  Is my understanding correct?
- Supply correct VCC voltage (ex. 3.3V or 4.2V)
- HOTRESET = High
- DCDCx_EN and LDO_EN = High
- one of VDCDCx or VLDOx goes down to around 90% of required output level

Could you let me know what status /INT will be when all of DCDCx_EN and LDO_EN are Low (while any PGOODZ<n> is unmasked) ?

A:

The /INT output will go low as following

   - /INT will remain low during power up, once all enabled rails are within regulation /INT will go high impedance

  - whenever any of the enabled rails falls out of regulation /INT will go low

  - when the PGOODZ register is read via I2C /INT will go high again even if the rails is still not within regulation.       

HOTRESET or VCC or EN_DCDC/ EN_LDO pins of the device do not have a direct impact on the /INT output

 In your described case, /INT should be high impedance