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Q: I attempting to exit from deep sleep where I expect VDCDC2 to remain on and the other rails to power up.In my configuration, register CON_CRTL1 = 0h5F = 8b1001111.To enter/exit deep sleep, I set CON_CTRL2 = 0h17 = 8b00010111 ( to enter ds), and CON_CTRL2 = 0h07 = 8b00000111 ( to exit ds). When exiting deep sleep, I measure a voltage drop on VDCDC2 when the other rails power back up as visible below. Is this expected?
A: Yes, this is expected because the PMU will perform a start-up from OFF state instead of an exit from deep sleep if bit DS_RDY of register CON_CTRL2 is not set before the PMU is put into deep sleep state.
The DS_RDY bit is described in the DEEP SLEEP Mode section of the datasheet on page 75.
To correct this, set CON_CTRL2 = 0h37 = 8b00110111 when entering deep sleep mode and CON_CTRL2 = 0h07 = 8b00000111 ( to exit ds). This will provide for exit from deep sleep instead of start-up from OFF.
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