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TPS2410/1EVM and TPS2412 ORing Controller - Output Blocking Abnormal
I find out a strange phenomenon about TPS2410/1 HPA204 EVM. All the board setup is factory default. When I provide 12V at PS1, Load has 12V output and it's reasonable. But PS2 also occurs about 6.7V. See the below wavform. It seems abnormal. It should be 0V at PS2. My customer also has the same issue using TPS2412. Could you help to explain this issue. Thanks.
CH1-PS1 Output Voltage, CH2-PS2 Output Voltage
There is a leakage path from Pin C to Pin A internal to TPS241x.
How does this leakage path being establish? I don't think it is normal for ORing application. It should be fully blocking from the output through into PS2. The voltage occure at PS2 will confuse our customer. Could you explain more detail about this phenomenon? Is it normal? Does it cause any unpredictable damage? Thanks.
This was answered before by Martin Patoka. I couldn't put the link in here so I pasted in his answer. To see the whole thread, search on tsp241 leakage
The A pin is connected to the charge pump output, and the switching thresholds are generated by running a little current out of the pins. Voltage on "open" input is probably due to some of both.
You could load the input with a little resistance to see if this helps your circuit. Maybe something like 4..99K.
For HPA204 EVM, when I load 2kOhm, I can still see the 1.8V at the input side. I think it is due to a large input capacitor. Even though, I still doubt the leakage is a "normal" behavior for general ORing application. Does it cause any side effect? Except adding dummy load at input side, do you have any idea to overcome this problem?
We have many customers for these parts. Some have mentioned this but there is no problem in operation of the parts. The ORing function is un-effected by leakage when both power supplies are connected.
From your 2k ohm example, it looks like a 900uA leakage. As the value of the input resistor is decreased, the input voltage will decrease. It will not be 0V.
If there is an objection to having a voltage present when the power supply is removed, it may be possible to power the TPS2410 VDD pin from pin A instead of from Pin C. This can't be done in all applications but it may be helpful in this case.
I have one question on TPS2411, one customer faced system cannot power up successfully, after change RSET (turns off threshold / reverse current cut off point) or increase C(FLTR) capacitor to 2200pF from 1000pF, both ways can fixed the issue on cusotmer board, my question is,
1) is it any spec for max value limation of C(FLTR)?
2) How about change to RSET, does any side effect? Thnaks
The operating spec maximum for CFLTR is 1000pF. It can be operated higher but that will increase the turn off time of the FET. Turn off time is less effected by higher voltage transients. Generally we want a fast turn off in case a power supply output shorts to GND. Slower turn off is not necessarily bad because it helps with power output droop at the switchover. You may want to access why there is a high voltage tansient. Often, this it is because of long power supply leads, lack of bulk capacitance, switching inductive loads, or other system issues. For high voltage transient, the fltr is a good solution.
Rset is the preferred way to de-sensitize unwanted turn off in a relatively low noise environment. This is usually used on the TPS2411 in a low load environment. TPS2410 may benefit from a negative turn off threshold but we usually recommend no RSET resistor for a positive .0025V turnoff threshold. T
If using RSET, it should be selected to be between -0.003V and -0.001V. When the turnoff threshold is negative, it takes some reverse current to shut off. Reverse current is current into the power supply. The reverse current is based on the RDSon of the FET and the turn off threshold voltage. Voff / RDSon can be a sizeable current for the small turn off time.
The way you choose to adjust these parameters is based on system specifications and actual functionality of the prototype.
Thanks, We spoken with Dell guy, they are studying and decide whether use R_SET with 90.9K & C_FILE with 2200pF solution;
He would like to know the issue root cause why ORING FET Gateis vibrated during start up, Gate is continuous turn on/ off
why increase C_FILT can fixed the problem? is it related IC loop unstable? Thanks
Please re-read this thread where I believe this has been answered. Also our correspondence on email. I've attached a paper from the product page that expalins the control systems for these parts. Please review these materials and help your customer make his selections.
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