Part Number: LM5050-1
Hi Expert,My customer has been trying LM5050-1 device as below set up.From their evaluation on the breadboard, they have 42V at output side, while they have nothing on input side.In that setup, voltage and current can be seen at input side.Since the Idss specification of their FET is around 10uA (max), then Vgs is 0V, so this behavior would be related to LM5050-1.Can you comment on this finding whether this is possible behavior?Also, do you have any ideas to minimize these voltage and current at input side?Do you have any ways to determine these voltage and current?Thank you for your support in advance.Regards,Ken
LM5060: Bi-directional Load Switche2e.ti.com/.../577512
Ken,Zero Leakage LM5050.pdf
When Vs is powered, and IN pin is floating as you describe or has a path to GND, a leakage path from Vs and OUT to IN and GND is described in the DS, section 7.1, pg 11. To eliminate this, Vs must be powered down. The attached differs from fig 29. Fig 39 elilminates the path to GND but will cause more current to flow out the IN pin. The attached is recommended.
In reply to Brian Daugherty:
Hi Brian,Thank you so much for suggesting the circuit for reducing leak current.Let me try to understand your circuit correctly.As my understanding, the Q4 (FET for "VS disable) is used to minimize the current input leak through the VS pin and this expects to be controlled externally. (Differ from OFF pin controll) It means if we can accept some sort of leak current, we just use OFF pin. However if we need to reduce the leak current as small as possible such as battery powered application, then it's recommended to use VS pin control. Correct?What about having a diode for IN pin in series in conjunction with Fig 29?Do you think this work?Thanks,Ken
In reply to Kenichiro:
LM5050_1 Leakage path.pdfKen,
You cannot put a diode in the 'IN' pin path as 'IN' is used with 'OUT' to detect reverse current and also regulate forward voltage. We tested fig 29 in the DS and found that by breaking the connection to gnd with the added Q2 and D3 it diverts the leakage that was going to gnd back into 'IN'. The best way to eliminate this is by disabling Vs per the schematic I sent. The OFF pin only disables the gate to the FET, with the body diode still able to conduct in the forward direction. This would happen anyway if Vin is lower than Vout. The LM5050 is still biased and will still have leakage.
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