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LM5070 with high input capacitor

Stefano Sivera
Prodigy 161 points
Other Parts Discussed in Thread: LM5070

Hi hall, 

In my application I'm using LM5070 for supply an application processor board, the schematics for POE stage is similar to the EVB: http://www.ti.com/lit/ug/snva104a/snva104a.pdf.

The load have continues pulse load that exceed the 400 mA of 803.2af for pulse load; I would like to decrease  this pulse with a large capacitor ( more than 300uF) connected on the input stage (C1,C2,C3).

During the POE plugging happens the inrush protection and the LM5070 input MOS go in linear conduction and limit the the current at 320mA (set with RCLP) for 60 ms (with  57V: max POE voltage).

In this condition we have 0.5 J dissipated on the device, but on the data sheet I haven't find any information to understand if it's capable of hold this power.  

Any suggestion ?
Thank YOU 

BR
STefano 

  • 0
    TI__Genius 10370 points
    Hi,

    I apologize that no one has followed up with your question. I'm going to close this thread, but if you still have a question please feel free to post a brand new thread instead of replying to this one. We will do our very best to respond within 24 hours to any new post you might have :-)

    Best Regards,
    Aramis P. Alvarez