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PD design - Oring of 12V adapter and POE+ at TPS23754PW Output

shwetha subraya
Prodigy 50 points
Other Parts Discussed in Thread: TPS23753
To be very precise as per "Advanced Adapter ORing Solutions using the TPS23753"

We are going for Keeping the PSE Powered With Options 2 and 3 . 

The external ORing circuit as per the attachment is used to select the 12V output between POE / adapter based on what is priority .

I need clarification on below points

1. When the adapter 12V is used ,using a diode and resistor in parallel will help to maintain 10mA bias current at the POE input keeping POE line alive 

2. When the adapter voltage is removed how much time the PSE will take for detection-> clasification -> start up -> powering the PD.

3. what modification in design needs to be done to skip the above powring of PSE link steps that can be skipped in the design.

4. Can the delay or buffer time required for the PSE to start powering be fulfilled using a Cap of some value at the output to keep the camera from powering off , If yes what are the parameters needs to be used to calculate the value. Is there any thumb rule to follow

Let me know if you need any clarifications.
POE_23754_ext_OR.pdf
  • 0
    TI__Mastermind 40120 points

    Shwetha,

    The datasheet has a section on 'smooth switchover' on page 31 when using adapters.

    There is a diode and resistor in series to keep the PSE on. DHLD and RHLD.

    With a lower voltage adapter there will be some voltage droop because the input of the converter needs to charge up to the PSE voltage. The time will depend on your total system solution and must be tested at that level.

    The smoothest solution is to use a 48V adapter and circuit on Figure 34 if the customer wants a seamless transition between adapter and poe. 48V adapters are common and are available off the shelf.

  • 0 in reply to Darwin Fernandez
    Prodigy 50 points

    Hi Darwin ,

     Could you please review the schematics and layout , the POE+ is endspan , as the ethernet in the cable assembly we are using doesn't give access to unused pins , We have adapter feeding 12V, cince 23754 aux Vin is 36V min , we Oring externally using mosfet and dioides  

    POE will be and adapter 12V will be enabled based on priority which will be done before hand , when either of them is switches the other should provide power to camera module without any delay .

    J1 connector is going to camera module , J5 is Power out from POE board to RF input in the housing .

    J2 is adapter power in 12V, 2A 

    3.3V is generated in the camera module which is used for SD card.

    Regards,

    Shwetha

    ZBC-2_POE_BOARD_17102014.zip
  • 0 in reply to shwetha subraya
    TI__Mastermind 40120 points

    Hi Shwetha,

    It looks like the PDF schematic only outputted half of the design. Can you send a full schematic PDF? Thanks!

  • 0 in reply to Darwin Fernandez
    Prodigy 50 points

    HI Daniel,

       I am here by attaching the block diagram for your reference 
    POE_Block diagram.docx
  • 0 in reply to shwetha subraya
    TI__Mastermind 40120 points

    Hi Shwetha,

    Schematic looks good! I saw no issues that stood out for me. I'm assuming you tested your application with the EVM. Did you test the EVM with your application load? Or a dummy load?

    For the T2P design, actual application uses the design on page 30 of the datasheet. This is to signal the load that the PSE can provide type 2 power levels. The EVM only uses an LED as visual confirmation that type hardware classification was done by the PSE. It's important for the load to know if the PSE can provide higher power so that the load knows not to operate at that higher power.

    I will do the board review next.

  • 0 in reply to Darwin Fernandez
    TI__Mastermind 40120 points

    For board review I recommend looking at the EVM and copying that design. The layout should be divided into 3 different sections with different gnd planes as you can see in the user's guide. There's the PD front end side (shield), the primary side gnd, and secondary side gnd.

    There should be no secondary ground plane at the front end of the PD (connector, diodes, and L4/L7). The shield ground (see user's guide).

    L4/L7 should bridge the PD front end with the primary gound. Again see user's guide.

    It's best to use SLUA469 design guidelines in your layout for optimum design. The EVM user's guide also has a good summary on page 8-9.