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How to change TPS23751 reference design to support 12V/2A output

Lonsn
Prodigy 180 points
Other Parts Discussed in Thread: TPS23751, TLV431A, PMP8812, TPS23752EVM-145, TPS23751EVM-104, CSD18533Q5A, TPS23752

Hi,

Currently we implemented 5V/4.5A POE+ design using TPS23751, and the design is same as TPS23751 evm(slvu754a). It works well.

Now we have a new requirement to implement 12V/2A output. We let the flyback transformer vendor change the secondary windings ot NA5730-AL to support 12V/2A output. Also the U5 TLV431A part has changed to support 12V.

The POE+ output is 12V now, but the main switch MOSFET Q3(Si7898DP) and flyback transformer are very hot(Compared to 5V design).

Are there any other parameters to be changed to implement 12V/2A design with TPS23751?

Thanks

  • 0
    TI__Mastermind 42795 points

    Yes, there will be a few other items to change. I'd recommend looking at the PMP8812 TI reference design (http://www.ti.com/tool/PMP8812?keyMatch=pmp8812&tisearch=Search-EN#Technical Documents) which converts the TPS23752EVM-145 (5V, 5A) to a 12V, 2.1A design (starting with the EVM and making BOM changes for the 12V output). Below are some key items to adjust on the TPS23751EVM-104.

    1. Output filter (C13-C17 change for rating and output capacitance.
    2. Q4 (synchronous rectifier) should be a 60V or most likely an 80V FET (you can use CSD18533Q5A).
    3. Error AMP passives around U5 and U4.

    FYI, the TPS23752 and TPS23751 have identical dc/dc controllers but TPS23752 adds the sleep mode function.

  • 0 in reply to Eric Wright
    Prodigy 180 points

    Eric,

    Thank you for quick response, we will have a try to replace Q4.

    Regards,

  • 0 in reply to Eric Wright
    Prodigy 180 points

    Hi Eric,

    According to your instructions, we have designed the 12V output version with TPS23751.7457.poe.zip Can you help to review it?

    Currently this new design has a problem, the flyback transformer working temperatue is very high(80 degree). is It the transformer issue or other circuit design issue?

    Thanks a lot !

  • 0 in reply to Lonsn
    TI__Mastermind 42795 points

    Hello,

    I will review with the engineer for PMP8812. Sometimes with a new transformer design, the switching FET phasing must be adjusted to reduce ON time overlap current between primary and secondary FETs (sometimes called "shoot-through" or cross conduction).

    As a bench test, try disabling the secondary side FET by removing R33. This will disable Q4 and allow D4 to be the rectifier (and eliminate any cross-conduction). Load the output at ~1.5A for some time and see if the transformer runs cooler.

    Some tuning of the Q2 (R22) and Q4 (R26) gate drive waveforms might be required if the above test yields a cooler transformer.

  • 0 in reply to Eric Wright
    Prodigy 180 points

    Hi Eric,

    Thank you for your quick response, I will test as your suggestions.

    Another question is about the adapter oring solution. According to SLVA306A, we use option 3 and want to implement adapter priority. You can see U9 opto-coupler and adapter 12V to control the DEN pin of TPS23751. I am not sure about following description in SLVA306A  " When used with a secondary-side synchronous rectifier, this circuit needs special attention to turn the rectifier off when the adapter takes over. This prevents power from flowing backwards and powering the primary side of the converter." Can you help review our design if any additional circuit to do after disabling DEN.

    Regards,

  • 0 in reply to Lonsn
    TI__Mastermind 42795 points

    The simplest way is to put a diode between the output of the POE regulator and the load.

  • 0 in reply to Eric Wright
    Prodigy 180 points

    Yes, understand. Thank you.

  • 0 in reply to Lonsn
    Prodigy 180 points

    After further measure the thermal data, we found that the most hot spot is as following:

    1: Bridge rectifiers HD01-T, 103 degree

    2: Secondary side FET CSD18533A5A, 97.8 degree

    3: Flyback transformer and following 0.33uH inductor , 75 degree.

    Environment degree is 25 degree.

    How can we decrease the FET heat?

  • 0 in reply to Lonsn
    TI__Mastermind 42795 points

    I had not noticed the HD01-T bridge in your schematic. For a type 2 PD you will need a better bridge, preferebly a Schottky (either discrete or integrated such as ).

    Were your conditions above measured at full output load? What is the input current with no output load? What were the results of the test where the synch rectifier was disabled? What is the DCR of the 0.33uF inductor you've chosen? How many layers does your PCB have (does it have decent copper area under the power parts)?