12V 150A Power Interface - Hot-Swap Controller, High side switch

Hi Hirotaka-san,

Is a device needed to only limit inrush current, or does it also need short-circuit protection?

If only to limit inrush current, then the LM5060 with a soft-start RC circuit would be a great choice.

To protect against a hot-short and start-into-short, it would be difficult to create a 24V 150A design due to FET SOA at 24V.

If practical, you can parallel two hot swap controllers controlling separate loads. This would reduce the current capability (split to 75A each) and load capacitance for each hot swap.

Also, is the 9-24V range including tolerances? If so, then the LM5069 would be a good choice. However, if you expect the bus voltage itself to run at 9V, then this would be too close to the POR threshold of the device and instead we would recommend the LM5060.

For the LM5069 we have a design calculation tool in which you enter your design requirements and part selection, then the tool checks for SOA margin.

The tool can be downloaded under the product folder --> Tools and Software --> LM5069 Design Calculator:

(bottom of the page)

Then we have this application note which pairs with the tool and explains the parameters, equations and methodology:

Lastly,

If the design is 12V typical and the max can be below 17V rather than 24V, then the LM25069 would be a good option:

http://www.ti.com/lit/ds/symlink/lm25069.pdf

Tool:

Thanks!

Alex

Hi Hirotaka-san,

Are you asking if we have a device which can source 20mA from the gate pin?

Currently all of our hot swap devices use an internal charge pump capable of up to ~20-25uA. Given the Ciss of most capacitors are <10nF, this should allow the MOSFET gate to charge at ~2.5V/ms. (I = C dv/dt --> 25uA = 10nF * dv/dt --> dv/dt = 2.5V/ms)

This is typically adequate for a variety of applications as during startup, inrush current limiting will be needed to protect the MOSFET and thus will not charge at 2.5V/ms.

If inrush current limiting is needed, then an external RC circuit can be added to slow down the gate charging further.

The R limits current into the gate pin when the device shuts off. Its value does not affect the equation Igate = Cgate dv/dt. Adding Css will add to Cgate and effectively slow down the dv/dt of the GATE. Since dv/dt of the gate ~= dv/dt of the output, this will create a constant inrush current limit for the output. The inrush current would be Iout = Cout * dv/dt.

Or to combine all equations --> Iout = Cout * Igate / Cgate.

The waveform would look as follows:

Thanks,

Alex

Hi Hirotaka-san,

Using the RC circuit will limit inrush current such that the FETs would not need to handle 225A of inrush current.

I am not sure why the 25uA charge pump would not be adequate to drive multiple FETs, though it may depend on the FET. We have tested one of our devices with a 24uA charge pump driving 6x PSMN1R2-25YL FETs for a 12V 120A design. When driving multiple FETs, we recommend adding a gate drive resistor of ~20ohms for the gate of each individual FET.

Attached is our design tool to get started if interested in our LM5069 device. The device features power limiting, such that during an during a short circuit, it can limit the FET power dissipation.

I began using our tool to make a 24V 150A design. The design is marginal if trying to protect a short with 24Vin at this high power level.  However, the same design being run at 12V typical should work and may also protect a short circuit or start-into-short circuit.

LM5069_Design_Calculator_24V_150A.xlsx

We have not tested these FETs with a wide VIN range such as max 24V Vin. If the actual input bus is at 24V, then it may risk damaging the FETs due to transients when plugging in or shutting off.

We have an application note which goes into detail on how to create robust, high power hot swap designs. It also explains the methodology behind our design tool.

Also you may visit our official website at  to learn more about our product offerings, tools and technical documents.

Thanks!

Alex

Hi Hirotaka,

Most hot swap devices can drive multiple FETs. In fact, adding more FETs can only make the control loop even more stable for our LM hot swaps.

So yes, the LM5069 can drive 10x PSMN1R2-25YL FETs. But to reiterate, using parallel FETs require an individual gate drive resistor of ~20ohms for each FET.

As for your question regarding our design tool, I made a mistake in my calculation earlier:

"Given the Ciss of most capacitors are <10nF, this should allow the MOSFET gate to charge at ~2.5V/ms. (I = C dv/dt --> 25uA = 10nF * dv/dt --> dv/dt = 2.5V/ms)"

The mistake is that Ciss was not the right value to use, as that has little effect during the phase when Vout rises. What should be used is the capacitance from gate to drain (or Crss in most datasheets). However, Crss is typically small so we neglect it in our tool for dv/dt calculations. If using 10x FETs, then the Crss will begin to add up, but overall it should not impact the margin of the design. It can only make dv/dt slower which is ok.

I will include a detailed explanation of Crss's role below in case you are interested.

Thanks,

Alex

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Generally, Ciss = Cgd + Cgs

and Crss = Cgd

But when Vout is rising in sync with Vgate, then there is 0 current going into Cgs.

Igs = Cgs * dv(gs)/dt    but dv(gs)/dt = 0, so Igs = 0.

Thus since Cgs is not charging with any current from the gate pin, it should not be used in the dv/dt calculation. 

And to resummarize the overall derivation:

I = C dv/dt.

Thus Igate = Cgate * dv(gate)/dt and I(out) = C(out) * dv(out)/dt.

Then since Vgate = Vout + Vth --> dv(gate)/dt = dv(out)/dt if we assume Vth is a constant.

When we put the two equations together we got I(out) = Cout * Igate / Cgate

So Cgate = Crss   (or Cgd)   + Csoft-start     and since Crss is small, we neglect it in our design tool.