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TPS27082 current

Hello,

TPS27082 implements a standard PMOS switch with the ability of slew rate, turn off speed turning through R1 and C1.

So does the above comparison between Q2 and Q1 mean we can completely ignore the tuning of Q2 in the way like tuning Q1?  If load switch is to be constructed using discrete components (to withstand higher voltage rating), of course we should choose Q1 which stands the maximum VIN.  

Hui

  • Hui,

    Answer 1: Q2 capacitance is not significant and can be ingored. Q1 and C1 capacitance is dominant.

    Answer 2: Q2 drain voltage must survive VIN voltage. Q1 drain and gate voltage must do the same.  Either BJT or MOSFET will work well. The purpose of Q2 is interface logic levels to VIN level  and to make a current source (with RS resistor). So consider temperature effects of BJT VBE and MOSFET VGS.

  • Hi Ron,

    "make a current source (with RS resistor)": the only utility of RS I realized is to adjust the final VGS of Q1, as described in datasheet "Configuring Q1 ON resistance". Are you actually referring to the same by the "current source"? Or else what is the current source meant for?

    I don't have solid knowledge on BJT VBE and MOSFET VGS physics. With reminiscent vague impressions, are you suggesting for MOSFET working above the VGS inflection point? What is case for VBE?

    Regards,
    Hui
  • Ron,

    "Q2 drain voltage must survive VIN voltage".

    If we have two diodes D1 and D2 of the same type, each withstanding VMAX. If we connect the two in series, do they actually stand VMAX or 2VMAX? If we have D1, D2 and D3...Dn?

    They math seems not clean because there is no pure resistance involved here and we cannot easily assume a current and sum the corresponding voltage on each diodes.

    Is this actually an involving problem novices should avoid?


    Hui
  • Hui,

    The RS resistor will see a maximum voltage of gate voltage minus threshold voltage of the NMOS. Because voltage is limited on the resistor, so is the current limited. The limited current sets the ramp rate on C1 capacitor to control the output rise time.

    There will be some temperature modulation the output rise time. However the change is not large and should cause any issues.
  • Hui,

    I do not see where diodes would help. Is your VIN unusually high?
  • In alternative designs I see RS placed above Q2. On 27082L datasheet page 5 it is explained that RS<<R1 minimizes Q1's gate voltage, increasing Q1's VGS hence reduces RDSon. For this purpose RS can be either put above A2 or below.

    For example, OnSemi AN places RS above Q2, so it is for most textbook examples.

    Is there any particular reason 27082L places RS below Q2?

  • Hui,

    With resistor above the capacitor voltage changes exponentially (1-e^-t/rc), RC time constant. With resistor below capacitor voltage changes linearly t*(Vgs-Vt)/RC.

    The effect on final PMOS Vgs is same for resistor above or below.
  • Ron,

    Is there any formula for rush current?

    Hui

  • Hui,

    Re-arranging the terms yield this equation.
    Slew rate = V/s = [C1 current] / C
    For the current, in parenthesis in original formula, to be fixed (ramp be fixed) just requires that VPL (pmos gate voltage) be fixed.
    This assumption is reasonable.

    I retract my exponential assumption.

    However I believe the first term should be (VPL - VIN)/R1 because this current opposes R2 current.
  • Ron,

    I also thought the note I referred to was not careful enough in choosing the signs.

    Is there any difference putting RS (in the top post 27082l picture) below or above the Q2 MOSFET?


    Hui

  • Hui,

    When on top dominant capacitor current is set by PMOS gate voltage/ R2.
    When on bottom dominant capacitor current is set by (NMOS gate voltage-VT(nmos)/ R2.
    Where (NMOS gate voltage-VT(nmos) is the NMOS source voltage.
  • Ron,

    We found rise time is good, just fall time too long.

    Hui

  • Hui,

    Output fall time could be a function of COUT and LOAD current. The TPS27082 can only turn off to stop new current into the output node. The TPS27082 will not drain the output capacitor charge.
  • Ron,

    Thanks for answer.

    I just experimented and replaced the output by a pure potentiometer with similar resistance. Whereas the rise time is several dozens of ns, fall time is more than 6 us.

    In this configuration the load is purely resistive. Is there still anything we can do to to decrease fall time?


    Additionally, if we replace C1 by a resistor, would it do any good to fall time AT ALL?


    Hui

  • Ron,

    Could you recommend any literature/app note on how particularly "fall time" (not rise time) can be reduced?


    Hui
  • Dear Ron,

    This is an important and urgent issue we need to solve. I sincerely wish to get a solution quickly.

    Hui
  • Ron,

    This at least on the surface appears to be a change in the order (of magnitude, etc.). Could this in practice be a significant improvement? And why this is not listed in the manual?

    Hui

  • Hui,

    For fastest turn off [try any/all].
    1) Lower C1. I know you already tried no cap.
    2) Lower R1. This helps pull the internal PMOS gate high faster.

    3) Add an external PMOS across R1 (source on VIN, drain on R1C1 node). The gate goes to ON/OFF input.
    This works if ON/OFF runs at 0V to VIN voltage levels. With 0V input new PMOS shorts out R1 and shorts internal PMOS gate to source.
  • Ron,

    I am looking at this solution carefully.

    Besides, some additional thought on why the datasheet (table 1) list only rise but not fall time:

    upon ON at ON/OFF pin, Q2 is turned on, so "explicit C1" or "parasitic capacitance (denoted by C1') between gate and drain" will be connected in serial with RS, so this open path (RS) allows C1 or C1' to be charged, and the voltage on C1(C1') changes by Vin*(1-Exp(-RS*C1*t));

    upon OFF at ON/OFF, Q2 is off so there is now only a path R1-C1 between (VIN and VOUT) for C1 to discharge. Granted we can make R1 small (as you suggested), the discharge of an RC circuit follows Vin*Exp(-RS*C1*t)

    The key difference is therefore between 1-Exp(-RS*C1*t) and Exp(-RS*C1*t) !! If we plot this we see that for example if we take 15% of a period T to reach 90% in the "ON" operation, we need another 85% of T to reach 10% in the "OFF" operation.

    So this exponential growth/decrease rate issue is the whole reason that fall time is much longer than rise time? Does it make sense?

    If so, I guess that (1) you solution will work;  (2) replacing C1 by a resistor will also work, perhaps even better.

    Could you give more thoughts on this?

    Hui

  • Hui,

    Yes, that makes sense. It is easier to turn on than off because the RC change is fastest at the beginning.
    I don't think placing a resistor at C1 location will help.
  • Ron,

    Ron Michallick said:
    Hui,

    For fastest turn off [try any/all].
    1) Lower C1. I know you already tried no cap.
    2) Lower R1. This helps pull the internal PMOS gate high faster.

    3) Add an external PMOS across R1 (source on VIN, drain on R1C1 node). The gate goes to ON/OFF input.
    This works if ON/OFF runs at 0V to VIN voltage levels. With 0V input new PMOS shorts out R1 and shorts internal PMOS gate to source.

    In numerical simulation if we make R1 excessive small (like 10 or 20ohm) this leads to convergence issues, however, the fall time does improve very significantly.

    For the real device operation (no numerical issue) if we could solve heat dissipation issue (such as using large area resistors), would it make sense that we replace R1 and RS with much smaller counterparts, such as R1/100 and RS/100, or even /1000, keeping the ratio is unchanged, in hope to get best fall time response?

    Please point out if this might lead to any other side effect / hazard and the necessary caveats.

     

    Hui

  • Hui,

    R1 can't be too low or the on VGS for the pass PMOS will be low.  |VGS| = VIN * R1 / (R1 +12.5k)

    I suggest helping the turn off externally. Here is an idea using a PNP or PMOS helper.