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LM5068MM-2, Min supply requirement for IC funcitoning

Other Parts Discussed in Thread: LM5068, LM5069

I'm hoping that someone can tell me what the Min. supply voltage allowed on the LM5068 is before the IC will start functioning.  That is what supply voltage is required before the IC will follow all faults and interlocks.  I know it requires 9V to release the internal interlock, is that also the minimum voltage that will keep the gate to source voltage to zero?

The function of this part is used to current limit, UV and OV protect another card on the motherboard.  That board is already installed, so when the power is applied to the main card, the LM5068 will be turning on and controlling the voltage to the other card.  So I expect there is a time that the LM5069 is not under control.  I couldn't find that in the specification sheet.

Thanks,

John

  • Hi John,

    The LM5068 keeps the external MOSFET held low while power is initially applied to the device. It does this by keeping its internal pull-down FET on during this initial part of its power on sequence. Then it will begin to charge a external timer capacitor with a 6uA current source until it reaches 4V (this features an insertion delay to allow transients to settle). Once TIMER reaches 4V, it will quickly discharge down to 1V. Only then, once the TIMER is at 1V, the LM5068 releases its internal pull-down FET and begins to charge the GATE pin with a 60uA output current source.

    So if I understand your question correctly, there is not a time where the LM5068 is not in control during this power on. It will keep power off until its insertion delay passes, and then it will begin to power up the output (in a controlled manner with its current limit).

    The detailed start-up operation is on page 11 of the datasheet:

    To give you an idea of the waveform, we have a newer, similar device which has an illustration of the power on sequence including what internal pull-downs are active and when.

    Figure 6 on Page 12

    Also we recently launched our new website for these devices at www.ti.com/hotswap which can serves as a landing page where you can find all of our technical documention such as application notes, design tools, training videos and latest product portfolio.

    Thanks!

    Alex

  • Alex,
    Thank you for the prompt reply and explanation. That is how I understand the part to work. Now I see that I need to provide a little more info to help you help me.
    We have several systems that right now seem to ignore the delay time we programed on the LM5068. It seems like as soon as the UV and internal UV interlocks are okay the LM5068 turns on the FET and output. This seems to happen around 8V input voltage. We have used a 0.022uF on the timing pin which should program about 14mSec delay before starting to turn on the FET. Our UV is set for 3.7V, which is a mistake, it should have been 7.5v. We are going to fix that mistake and then complete the test again to see what happens, but from the traces we see I don't get how the timer is not delaying the turn-on. I'd send you the pictures, but I don't see how to attach files in this form.
    Thanks again for your help and comments.
    -John
  • Hi John,

    At 8V Vin, this is below the undervoltage shutdown (Vuvs) of the part. Thus the first interlock criteria for beginning to charge the gate is not satisfied.

    (Page 11 of Datasheet):

    When power is initially applied to the card, the gate of the external MOSFET is held low. When certain interlock

    conditions are met, a turn-on sequence begins and an internal 60 μA current source charges the gate of the

    MOSFET. To initiate the start-up sequence, all of the following interlock conditions must be satisfied:

    • The input voltage VDD - VEE exceeds 9V(VUVS)

    • The voltage at UV is above 2.5V (VUV)

    • The voltage at OV falls below 2.5V (VOV)

    • The voltage on the Timer capacitor (CT) is less than 1V (VTLVT)

    • The GATE pin is below 0.5V (VGLT)

    At this voltage, the device should be in "disabled mode" and keep the gate off. If the UV is set below 9V, I would not expect it to have an effect.

     

    What is the input voltage range you are testing with? A waveform of Vin, Gate, Vout and TIMER (all can be referenced to VEE) would help sort out any issues.

     

    We recently upgraded our E2E Forum but it has made it difficult to upload images.

    To upload a waveform please select "Reply" and then "Use Rich Formatting" on the lower right corner of the reply box. Then you may type a response as usual and click on the image icon in the middle-bottom of the rich formatting toolbar. This is an "INSERT MEDIA" link in which you can upload any document (.jpgs, .pdfs, .xlsx, etc).

     

    Lastly if you still have trouble uploading a waveform, we have encountered some issues with IE and found it works better with Chrome or Firefox if you have that available.

     

    Thanks!

    Alex

  • Alex,

    Here are some traces I can share.  Our testing is remote and I won't have more until next week.

    RGray_20150116.pdf

    on the first page are the CPU card power +/- 15 supplies (identified as un buffered N15V and P15V.

    un buffered N15V goes to VEE on the chip.  Vdd goes to GND.   All voltages are measured from GND.

    Buffered N15 comes from the FET being driven from LM5068.  this first page shows the FET turning on about 1msec after the N15 getting to 8V or 9V, kind of hard telling.  Say that the voltage was 9V, then I should still have 14 mSec before the FET was to start turning on.

    Second sheet has the Gate voltage shown.   That shows that the Gate voltage is starting to turn on just after the N15 unbuffered supply gets to 8 or 9 volts.

    Next attached file is the schematic.

    RGray_Schematic.pdf

    -John

  • Alex, one other thing. I just noticed that I'm not complying to the absolute max of OV/UV to Vee shown on page 4 of the specification. But it says clamped. Does that mean the IC clamps it? or do I have to clamp it? Does this damage the IC?
    UV/OV (Clamped) (UV/OV to VEE) - 8V absolute max.
    With the current resistor divider I get 10V when the N15 goes to -15.

    Thanks,
    -John
  • Hi John,

    I will need some time to look over everything more closely. I will keep you updated early next week, but a waveform of GND (A in schematic), GATE, N15V buffered and TIMER (all referenced to VEE - N15V Unbuffered) would be help in troubleshooting.

    Also I noticed on the schematic there is a Cgs cap, C177. This could damage the device, as 0.1uF holds quite a bit of energy and all this energy would be discharged into the GATE when it shuts off, which could damage the GATE pin of the IC. Most FETs have a Ciss of <10nF, which is an order of magnitude less. Removing C177 and replacing with a new part may help.

    Thanks,
    Alex
  • Alex,
    Thanks again and please see what you can find. but again I won't have anything until next week since troubleshooting is being done 1/2 world away.
    C177 is very near what the data sheet requires (0.022uF). But we had to change the position. N15 had a hiccup mode and we had to move it to the position that it is now and increase it so that the device turned on. Otherwise it might have not turned on. The issue is where the cap is hooked up. in the Data sheet it is across the sense resistor. So gate voltage would decrease when an inrush happened, which would start to turn off the transistor. This negative feedback produced bad results on our card. I have not had any issues having that size of cap there before. I can do that change a little later if other things don't pan out.
    Also the cap helps the configuration since the gate voltage and drain voltage are going in opposite directions and there is some neg feedback from the drain.

    -John