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LM5060 Impedance between the GND pin and the other pins

Tomoaki Yoshida
Expert 2200 points
Other Parts Discussed in Thread: LM5060

Hi,

 

I would like to know the impedance between the GND pin and the other pins, nPGD,UVLO,OVP,EN, etc.

Please tell me the information if there is.

It is necessary for us to check the current pass at reverse battery condition.

 

Best regards.

  • 0
    TI__Genius 12380 points
    Hi Yoshida-san,

    The LM5060 has ESD protection diodes which result in an impedance of a diode drop from GND to those pins. That's why the ABS_MAX spec lists -0.3V, because if you put a direct reverse voltage greater than -0.3V across these pins (without limiting the current), then the device will break.

    However if you limit the current to -10mA, or at least below -25mA, then the device should be ok. Check out the footnotes within the ABS_MAX spec table on page 3 of the datasheet.

    As a guideline, you can check out Figure 38 on page 26 of the datasheet as well. It uses resistors to limit the current during reverse polarity condition.

    Thanks!
    Alex
  • 0 in reply to Alex Triano
    Expert 2200 points

    Hi Alex,

     

    Thank you for your reply.

    We had designed in reference to figure 38.

    Also it is insertion resistance for the current limit at the time of reverse connection.

     

    I am concerned  that there is current pass to EN pin or nGND from GND pin through the inner diode or test circuit.

    EN pin and nGND pin are connected to interface and VDD of microcomputer.

    Is there the situation like that?

     

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida
    TI__Genius 12380 points
    Hi Yoshida-san,

    Is the microcontroller open drain? If so, then the reverse polarity may cause a leakage path through the microcontroller's open drain FET's body diode.

    This should still be ok, since the current is limited by the resistors. If you are concerned, then you may add padds for a small schottky diode from EN to the microcontroller with an etch shorting the pads (as a placeholder for prototyping). Then if there is a concern during your testing, you can simply cut the etch and then populate a diode to test (then do the quick fix in layout for production).


    If the MCU is not open drain (and is push-pull), then this should connect to an external NFET which then ties into the UV pin. This would then serve as an open-drain signal, and once again should work.

    Thanks!
    Alex
  • 0 in reply to Alex Triano
    Expert 2200 points

    Hi Alex,

     

    Thank you for your reply.

    I understood that current leak path to EN pin from MCU's FET body diode.

    I will check that the MCU is open-drain or push-pull.

    Can you think other current leak path from other pins in using like figure.38?

     

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida
    TI__Genius 12380 points

    Hi Yoshida,

    No I do not see other leakage paths.

     

    A couple of months ago, I captured waveforms of testing the Figure 38 circuit. See the PPT attached:

    LM5060 Reverse Polarity Protection.pdf

     

    Thanks!

    Alex

  • 0 in reply to Alex Triano
    Expert 2200 points

    Hi Alex,

     

    If the microcontroller has body diode, how much the leak current will be supposed?

    Vbat will be -12.5V at reverse polarity.

     

    I would like to estimate the delay time from Enable is turned high to the Gate will be over Vth.

    Simply, Can I calculate the time is charge the parasitic capacitor of gate by Igate?

    We're worried about other factors are involved.

     

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida
    TI__Genius 12380 points

    Hi Yoshida-san,

    The LM5060's EN delay is not spec'd in the datasheet, but it should be on the order of microseconds. After this brief delay, the time it takes to charge up to the 5V Vgs-th (the point where the IC resets the TIMER during startup) would be as you mentioned, the parasitic capacitance of the MOSFET's GATE being charged by a 24uA typical constant current source (charge pump). Overall, we suggest sizing the timer to be at least 2-3x the typical startup time, due to variance in the gate charging current, the Vgate-th value, mosfet capacitance and timer thresholds. To get a rough estimate of the typical startup time, you can look at the MOSFET's charge curve to see what value it would take to get to 5V Vgs. Most MOSFETs will be around 30-100nC which would take ~1.25ms - 4ms (since I = coulombs/second --> 24uA = 24uC/s = 24nC/ms). If the design uses parallel MOSFETs, then this time would increase.

    Edit: As for the EN current through the microcontrollers body diode in a reverse polarity condition, that would only occur if the microcontroller is also seeing -12.5V and there is a pull-up resistor from Vin to EN. If so, then its open drain FET's body diode would conduct, and the leakage current would be roughly Vin / Ren where Ren is the pull up resistor used from Vin to EN for the LM5060 design.


    Thanks!
    Alex

  • 0 in reply to Alex Triano
    Expert 2200 points

    Hi Alex,

     

    I would like to check the pull-up resistor between Vin and EN that you said.

    I understood the pull-up resistor means external and there is not internal pull-up resistor.

    Is it correct? 

     

    Best regards,

    Tomoaki

  • 0 in reply to Tomoaki Yoshida
    TI__Genius 12380 points
    Hi Tomoaki,

    Yes that is correct. Internal, the EN pin has a pull-down bias current of 6uA (spec'd in datasheet, page 4). There is no internal pull-up resistor.

    Thanks,
    Alex
  • 0 in reply to Alex Triano
    Expert 2200 points

    Hi Alex,

     

    Thank you for your reply.

    I would like to know Vgs at low Vin condition.

    For example, when Vin is 5.5V, how much  is lowest Vgs?

    If the efficiency of the charge pump is 90%, Vgs is 9.9V.

    However , if it is 80%, Vgs is 8.8V.

     

    Also, at low Vin case like that, is there a problem of heat of IC to fell the efficiency of the charge pump?

     

    Best regards,

    Tomoaki

  • 0 in reply to Tomoaki Yoshida
    TI__Genius 12380 points

    Hi Tomoaki,

    We are digging into this.

    First we are checking if this is tested within our final test program (Vgate at min Vin, 5.5V).

    To give some insight into this device's charge pump, it is a 3-stage charge pump. The internal regulator voltage is about 5V. Each stage of the charge pump generally has a diode drop, so this is where the Vgate = 12V typ parameter comes in (3x 5V - 3x Vdiode = ~12V).

    So the question is, what is the dropout voltage of the internal regulator. If Vin = 5.5V, will the internal regulator output 5V? The answer is probably no.

    About a year ago, I provided you with a waveform on this E2E thread (last page):
    e2e.ti.com/.../1290668

    With 5.5V Vin, it had about 10V Vgs versus 12V typical at higher Vin. This means the internal regulator is outputting less than 5V.

    So we will first check if this is tested in our final test program. If it is not, we can run units in our lab by increasing Vin in increments (5V, 5.1V, 5.2V, 5.3V, etc.) and plot a Vgate vs Vin curve. This would only be one unit, but would give us an idea of how linear the internal regulator performs.

    Overall, in order for there to be minimal Vgs (less than 5V at 5.5V Vin), the internal regulator would need to be down to ~2.7V (3x 2.7V - 3x Vd). We see this as very unlikely, as that would mean quite a variance in the regulator dropout voltage. But, running this test should give us initial guidance on how the dropout voltage looks.

    Thanks!
    Alex

  • 0 in reply to Alex Triano
    TI__Genius 12380 points
    Hi Tomoaki,

    Good news.

    So we were able to find char data which shows the behavior of Vgate (which means the Vgs voltage) at different input voltages and temperature.

    We have data for VIN = 5.5V, 14V, and 65V.

    For VIN = 5.5V, the nominal Vgate voltage (which again means Vgs voltage in this context) was ~10.2V at 25C and ranged from ~10.5V (at -40C) to ~9.7V at 125C.

    We do have limits in our final test program. So for all silicon being shipped, the gate voltage is measured at 25C, with limits of 9.69V to 10.87V. If silicon tests outside of this range, it is rejected.

    Hope this answers your question.

    To close out your question regarding charge pump efficiency concerning heat dissipation, it is minimal. At low Vin, any charge pump inefficiency would be in the range of uA's, not mA's, so it would not be a concern. I also confirmed this with our design team.

    Thanks!
    Alex