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TPS2492 Overcurrent function

Troy MacDonald
Prodigy 60 points
Other Parts Discussed in Thread: TPS2492

Greetings,

I have a TPS2492 set up with an overcurrent point of 50A.  

When a load of >50A is applied, the gate voltage reduces, the fault timer ramps, and the MOSFET is turned off with out any damage.

If the overcurrent threshold is approached slowly, there is load point of about 49.5A to 50A where the FET gate voltage begins to reduce, however the timer does not start to run. If this current is maintained for an extended period of time, the result is violating the SOA of the FET (indefinite time spent in linear region). My power limit is set to 200W at Vprog, Since the Rdson of the FET is 1.5mohms, running at 49A is not near the Plim set by the voltage divider, so I'm confused why constant power engine begins lowering the gate voltage prior to the overcurrent being recognized and initiating the timer that is meant to protect the FET. I have verified this by sitting at 49A for extended periods of time with no issues.

Am I overlooking any features that would cause the constant power engine to lower gate voltage just prior to the overcurrent condition being recognized?

Thank you for your help.

Troy

  • 0
    TI__Genius 12380 points
    Hi Troy,

    Welcome to the E2E forums! I hope you have a great experience here, and thank you for considering the TPS2492 for your project.

    So, we understand your concern. For terminology below, I will refer to Vsns as the voltage across the sense resistor.

    So basically once the hot swap controller is running and the input - output voltage is minimal, then the hot swap GATE should remain high until current rises and Vsns approaches the regulation point of around 50mV typical for the TPS2492. Then the TIMER should start running, and then the GATE should regulated to help keep the current below the current limit.

    But to get in further detail of what would happen if you very slowly increased current / Vsns towards the 50mV point:

    1. First, GATE voltage will begin to decrease very minimally. This has to do with the internal IC characteristics. However the GATE should still be high enough to keep the MOSFET fully enhanced.

    2. Eventually, the TIMER will begin to source current. It should begin to source current while the MOSFET is still fully enhanced (before the MOSFET is being regulated).

    3. If the part did not time out yet, then eventually the Vsns will be high enough (50mV typical) to cause the GATE voltage to decrease to the point the MOSFET is no longer enhanced and is instead being regulated in a saturation region (high Vds voltage) and a high power dissipation state.

    From the test you conducted above, how much did the GATE voltage drop without running the TIMER? If it was just a volt or two, then the MOSFET would still be on and with a low Rds-on.

    FYI - I will be out of the office for a week, so a colleague will help out as needed but please expect a delayed response.

    Thanks,
    Alex
  • 0 in reply to Alex Triano
    Prodigy 60 points

    Thanks for your reply.

    The gate voltage drops as low as 5V. I do not have a great scope capture of this, but if the trace is observed in a "free run mode", the gate voltage is seen to drift slowly between 5V and 10V. Normal on voltage is 13.5V. It is observed on a time scale in the ballpark of 30 seconds, and the cumulative effect is the FET temperature increasing over that time period. My apologies for not having a good scope capture, but the timer pin voltage does not begin to increase here even though the FET gate voltage is low.

    Maybe the gate voltage begins to drop and reaches a point where Rdson increases prior to the timer circuit sourcing current. Then current through the FET would begin to be limited by Rdson. After that the current drops slightly away from the 50mV set point, and the gate voltage will increase to full on with the current going back to the point where the gate voltage begins to droop again... Do you think this a feasible situation if the gate voltage doesn't drop "minimally" and in fact drives the FET in the linear region?

    For reference, this scope capture shows what I think the expected behavior is when stepping to a load of about 52A. Time scale here is 2ms/division. Current is limited, gate voltage drops to around 4V, and the switch disables when the timer pin reaches 4V.

    CH1: TIMER (1V/div)

    CH2: FET Source applied step current(10A/div)

    CH3: Source to ground voltage (20V/div)

    CH4: FET Gate voltage (5V/div)

  • 0 in reply to Troy MacDonald
    TI__Genius 12380 points
    Hi Troy,

    I did not see the scope image attached. You would need to hit the "Use Rich Formatting" button on the bottom right corner of the reply box, then insert image. Sometimes our website has compatibility issues with specific versions of Internet Explorer vs. Google Chrome.

    Do you have any additional circuitry on the GATE? Any zener diodes, or any resistors from GATE to Source or Gate to GND? Are the scope probes 1M or 10M? Just keep in mind the gate sourcing current is in uA's, so any resistance paths can affect the gate voltage.


    Thanks!
    Alex