Hi All：
We are now designing a product with DC power supply. We choose TPS2419 to manage the backup battery supply .So that TPS2419 will driver the N-MOS to swith on the battery supply when the DC is power off. The schmatic shows as blow. When Va>Vc and Va>9V, the gate will output 16V. But when Va>Vc and Va<9V. the gate pin just stay low whenever Va>Vc or Va<Vc. Why does not the gate pin output high level when Va>Vc as well as Va<9V?
A few things to work:
1) In a blocking FET configuration, the FETs should be common source vs common drain in your schematic.
2) The TPS2419 has its bias (Vdd) tied to 'C', which is tied to the output when using back to back FETs. In a normal single ORing FET configuration, bias would come from the 'A' side through the body diode, but their will be opposing diodes in a back to back configuration. Unless there is voltage on C all the time, you will need to change to another device.
I think you had some success in the VA >9v setup because there is some leakage current from A-C that actually biased the device though the 'C' input, but that will vary.
Try using the TPS2413 that has Vdd separate from 'C' and configure per the attached diagram (right out of the TPS2411 DS, pg 22).
Brian
You mean the charge pump can't get bias supply from back to back FETs ? And the TPS2413/TPS2411 get supply form VDD pin ? If I replace the TPS2419 with TPS2413. and change the pin configuration for VDD and RSET.See as the schematic below. Will it works?
