Other Parts Discussed in Thread: TPS23754
TI evaluation board TPS23754EVM-383 is a 4 layer board with middle two layers for routing. Besides routing, its top and bottom layers are copper filled with split ground planes & doing SMT.
We are evaluating a 4 layer design but with different stacking. Middle two layers are split power & ground planes. Top and bottom layers are doing routing & SMT.
1) Is TPS23754EVM-383 layout stacking a MUST to bring up the TPS23754? Or it is more for EMI containment?
2) What do you think about the layout stacking like ours?
3) (Side question) If the power pad (VSS) is connected to RTN ground plane in accident, could this be the primarily reason to fail the detection? (The chip still has VSS pin 10 to return current to its source - the PoE side possibly?)