• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 63 subscribers
  • Views 1109 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS23861EVM-612: TPS23861+TPS2378 Startup Fault

Jack CCY
Intellectual 1695 points
Part Number: TPS23861EVM-612
Other Parts Discussed in Thread: TPS2378, TPS23861, TPS2378EVM-105

Hi Sir,

I used TPS23861EVM and TPS2378EVM to test the start up fault. The electrical load is linked to TPS2378 directly with 0.45A to simulate over current startup.

And TPS23861 worked in mannul mode by USB GUI. The 1st channel is Vdrain-GND voltage and 2nd channel is Vgate-GND. My question is why there is a pulse during the Tstart(60ms)?

  • 0
    TI__Genius 15655 points

    Hi Jack,

    Can you confirm you used TPS2378EVM-105 for this test? I will need to do some test in lab and get back to you soon. Thanks.

    Best regards,

    Penny

  • 0 in reply to Penny Xu
    TI__Intellectual 1695 points

    Hi Penny,

    I did use TPS2378EVM-105, and the electrical load with CCL 450mA is linked to VDD and SRTN directly.

    Before TPS23861power on button, the 450mA load is ON.

    Thanks for testing.

    Best Regards

    Jack Chen

  • 0
    TI__Prodigy 160 points

    Hi Jack,

    When the PD is powered on, your load tries to allow for 450mA of current. However, during the inrush period, the external FET of the PSE is used as the foldback mechanism to limit the current to ~425mA (from Figure 57 of TPS23861 datasheet). Thus, the reduction in VGATE occurs which causes the rise in the VDRAIN voltage. This increasing drain voltage lowers the PD's VDD-VSS voltage to the UVLO threshold of the PD causing the load to shutoff. Since the current drops back to zero from load shutoff, the inrush current protection is removed and the gate voltage returns to its full value causing the gate pulse in question. After current is allowed to flow again, the foldback is reasserted and causes the second reduction in VGATE which remains until the end of the Tstart period.