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LM25066A: Power Up Sequence

Christopher Arntzen
Intellectual 580 points
Part Number: LM25066A

Referencing the datasheet, pages 20-21 and Figure 32, regarding the Power Up Sequence:

In Figure 32, there is a time period between t1 (Insertion Time) and t2 (In Rush Limiting), where the FET gate is charged with the 22uA source, and the text reads "the GATE pin then switches on Q1".

I have the following questions with regard to this time:

  1. What is meant by Q1 switches on? Is it when the Miller capacitance is fully charged? Is it when drain current starts to flow?
  2. Is current limiting / power limiting happening during this time?
  3. Does the fault timer start at the end of t1 or the beginning of t2?  Figure 32 shows that the fault timer starts at the beginning of t2, but just want to be sure.
  4. If the fault timer starts at the beginning of t2, how does the LM25066A know that Q1 is turned on and that it should start the fault timer for t2?

Thank you,

Chris Arntzen

  • 0
    TI__Expert 5940 points

    Chris,

    1+2.  Gate turn on is when 22uA current source is sent to the Gate of the FET.  This current charge both Crss and Cgs until Vth of the FET is reached, at which point only Crss is charging.  After Vout rises to its final value (Vin), then both Crss and Cgs is charged on the FET.  During this period, both CL and Pwr Limit control is active. 

    3.  The fault timer is only active is CL or Pwr Limit are active, which it will do if no dv-dt circuit is present and is shown in fig 32.  If dv/dt control is used (see front page of DS with D1, 1k, Cdv_dt, Q3), then CL and Pwr Limit will not activate (if Cdv_dt is selected correctly) and the timer will not active.  Per the discription, the timer is active during the insertion time t1, which is used to allow the insertion of a board to ride through transients on Vin and the initial chare of Crss when Vin is present and gate is held low with the 2mA pull down.

    4. t2 is when the gate of the FET is active.  The figure shows a CL start with gate held in a linear region to limit the current.  If CL persists through the Ct timeout, the LM25066A will shut off the gate.  If Cout charges during the Ct timeout period, with current decreasing below CL setpoint, then the gate will will continue to rise as shown in fig 32 for a normal power up.  CL decreasing is the normal indication to the LM25066A that normal power up has occured, as is the PG signal when Vout rises above the threshold.

    Brian

  • 0 in reply to Brian Daugherty
    Intellectual 580 points

    Brian,

    Regarding #3:

    I will not be using dv/dt control.  Figure 32 shows the 90uA fault timer current ramp starting at the beginning of t2; however, you stated that the fault timer is active when CL or PL are active, which is true for the period between the end of t1 and the beginning of t2.  Figure 32 shows the TIMER Pin flat between the end of t1 and the beginning of t2, which seems to contradict what you stated.  Should Figure 32 show the 90uA fault timer current ramp starting at the end of t1?

    Thanks,

    Chris

  • 0 in reply to Christopher Arntzen
    TI__Expert 5940 points

    Chris,

    Gate begins to rise at the end of t1.  This is when the 22uA current begins to be sourced from the LM25066A.  Crss and Cgs are both charging.   Once Vth is reached, Vout begins to rise and the current increases to the CL point, Vgs operates in the saturation region of the FET with current regulated to the CL setting.   The diagram depicts a CL condition at t2 with inrush current regulated to the CL setting and the timer active as soon as CL is reached.  So the gate begins to turn on between t1 and t2 with current ramping to the CL setting after Vth, but no timer until it reaches CL. The timer is only active when CL is reached, at t2.  

    So the period between t1 and t2 is not a CL or a PL condition and the timer is not active.  The diagram is correct, it shoud not show the timer active at t1 as you suggest.  At t2, the current reaches CL and the timer activates.  I highly advise you take advantage of the excellent excel tool you can download from www.ti.com/hotswap to assist you in your design.  There are a lot of app notes and app videos that are extremely useful in the link.

    Brian