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TPS23754EVM-420: POE Design for 24V

Part Number: TPS23754EVM-420
Other Parts Discussed in Thread: TPS23754,

Hi,

Iam planning to design 24V/1.25A POE design using TPS23754 for our project.

I have searched several TI design but could not find 24V/25W, then i have followed suggestion given by TI application engineer for POE for 24V/1.25A using 

TPS23754EVM-420  by changing Transformer that can support 24V and some changes compared this EVM.
Please suggest me any mistake in my design .
I have attached Design pdf doc.
Regards,
Namith HL
  • Hi Namith,

    Looking at the schematic:

    Your aux input should connect to the secondary
    D10 is backwards
    D17 is backwards
    Your T2P signal should be used to tell your actual load what type of PSE is connected to the PD so that the PD can adjust the output power to accommodate the Type PSE that was connected.

    Regards,
    Darwin
  • Hi Darwin,

    Thanks for quick reply,

    I have not worked on POE design before so please suggest me some information becoz iam runing out of time by understanding POE design.

     As you suggested after reviewing my schematics changes to be done are:

    1) D10 backwards,D17 backwards ..is it i have to reverse the diode?

    my specification:

    • POE output voltage and secondary dc supply 21-30V shall be diode OR'd with POE supply as an alternative means of powering the unit
    • According to loading on power amplifier  2 modes of POE operation  i.e 802.3af (POE) and 802.at(POE+) as Different speaker load to be connected .
    • status LED on the PCB whether POE or  Secondary DC is in use.
    • speaker configuration will be 20W load and 6W load.
    • 6W Speaker use POE ( 802.af)
    • 20W Speaker use POE+ (802.at)

    my doubts in poe design:

    1) changes as u have suggested to change 5V/25W Synchronous flyback design are sufficient for our requirement 24V/25W

    2) I have changed Transformer that can support 24V/1.25A

    3)Is secondary gate drive (GAT) is not required in 24V DESIGN?

    4)TPS23754 -420EVM  has secondary gate drive ,and Q1,T3,Q3 and D17  whether all this not required?

    5) my main doubt T2P usage what is the function of T2P?

    6)AS my secondary i/p is 21-30V we are planning to convert 24v and then diode OR 'd with POE as alternative means of powering the power amplifier load.

    7)where to give my secondary 24V output.

    now i have attaching changes that u have told included in pdf ,kindly suugest me any other changes to be done,.

  • Hi Namith,

    Yes it should be reversed. This is because the diode is on the low side. 

    1,2. Please see attached to clarify the 24V schematic.HPA420C_24V_sch.pdf

    3. Secondary gate drive is not required because it is a diode rectified flyback.

    4. You can remove Q1,T3,Q3 and D17 

    5. T2P will let you know if af PSE is connected or at PSE is connected. If af then T2P will be high, if at then T2P will be low. You should use this to know to change load output power between 6W and 20W.

    6,7. Yes I agree it should be or'd with the 24V output of the converter (on the secondary). But in the schematic it was not referenced to secondary ground.

    Unfortunately, I do not see an attachment for new schematic, can you attach for review? Thanks!

  • Hi Darwin,

    I have attached schematics file ,kindly review it.

     I have connected my Auxiliary dc voltage and poe output diode (OR'd) with same ground ,i hope this is what you have suggested earlier

    1) For T2P side is there any changes to be required?

    2)how to provide status led which i/p is available poe or Auxiliary voltage?

    3)If two i/p available at same time what is probality? any damage to PD

    4)Please suggest any other modification to be required in schematics?

    if nothing is can i proceed for further ,becoz already i wasted so much time in this  design

    5POE design for ti review.pdf)Our requirement maximum 22 W can this design withstand for power?

  • NOTE: POE secondary o/p and Auxillary o/p voltage GND are same forgot to mention in above.
  • Hi Namith,

    For your adapter input, you probably should have the secondary ground connected after L24. This way your filter will be more effective.

    1. The opto design is correct, you now have a signal on U27 that will tell you if an AT, or AF PSE is connected to your PSE. It's up to you on how to process this signal to either output AT power or AF power at the load.

    2. Looks like you have already status LED D30 (PoE) and D45 (aux) that shows that PoE or aux is connected.

    3. If both inputs are available, since it's diode or'd, the higher of the voltage will provide power to the load while the other will block the reverse voltage. There should be no damage to the input.

    4. No other modifications other than my comment above.

    Regards,

    Darwin

  • Hi Darwin,

    I would like to ask final queries before i will proceed further for pcb layout, i hope you will not mind.

    • Resistor values for R (FRS) = 69.8 k, since 250Khz switching frequency.is it correct?
    • what is the value for DT i.e R(DT) since we not using secondary gate drive (GAT 2) ?
    • Datasheet says Connect DT to VB to set the dead time to 0 and turn GAT2 off.? what to do this RDT?
    • What is the value for BLNK? RBLNK=80.6K? is it correct ?
    • what is the efficiency of design?
    • what is the maximum current for this design?1.02A right
    • becoz i need minimum 1A current for my load
    • can you share layout guidelines for pcb layout link for this design if have
  • Hi Namith,

    My goal is to make sure your design does smoothly by answering any questions you might have. Please see my comments below.

    • Resistor values for R (FRS) = 69.8 k, since 250Khz switching frequency.is it correct?

    [DF] That's correct, 250kHz is sweet spot for maintaining high efficiency given the poe input voltage range and power levels.

    • what is the value for DT i.e R(DT) since we not using secondary gate drive (GAT 2) ?

    [DF] DT should connect to VB to turn if off.

    • Datasheet says Connect DT to VB to set the dead time to 0 and turn GAT2 off.? what to do this RDT?

    [DF] RDT should be removed.

    • What is the value for BLNK? RBLNK=80.6K? is it correct ?

    [DF] RBLNK value is correct

    • what is the efficiency of design?

    [DF] Higher voltages, the synch flyback efficiency will be similar to the diode rectified flyback (with low enough Vf). In addition, a higher output voltage will yield a slightly higher efficiency (for the same input). So I would expect similar efficiencies as the EVM ~85-87% (end-to-end)

    • what is the maximum current for this design?1.02A right

    [DF] That is correct. Note, it was designed for 1.02A; however, per the IEEE standard, the max input power of the PoE PD is 25.5W. So while the converter itself can go up to 1A with a 48V adapter, when PSE is plugged in, the max output power of the converter should be limited to 25.5W x (end-to-end efficiency).

    • becoz i need minimum 1A current for my load

    [DF] Given the above equation, with 25.5W and 85% efficiency, the output current will be ~0.9A. You might get away with 1A if you have a shorter cable; however, if you want to stay within the IEEE standard, 25.5W is what you should design around.

    • can you share layout guidelines for pcb layout link for this design if have

    [DF] Please see below link.

  • Hi Darwin,

    I have attached updated schematics as per your suggestion  , kindly have look at this before layout.


    still i have doubt on T2P

    If T2P is high then it is 802.3af(POE) and T2P low then it is 802.at(POE+)

    our load is different speakers like 8ohm 20W  and 8ohm 6W,

    1. Question:If POE I/P available T2P  on the chip will recognize whether it is POE or POE+  right?
    2. becoz based on the input our load has to change i.e speaker configuration by seeing the T2P status?MAIN BOARD _ 05_POE.pdf

  • Hi Namith,

    1. That's correct.

    2. That's correct. Your load must use T2P (through an opto) and change its power to accommodate the PSE power based on T2P going HIGH (.af) or LOW (.at).

    Regards,

    Darwin 

  • Hi Darwin,

    I have question regarding Classification Resistor(CLS) pin ,in my design i have connected 63.4 ohm for  class 4 i.e min 13W and max 25.5W Power at PD.

    This means minimum power that the power device can deliver 13W and maximum 25.5 W is it my understanding is correct?

    If that is the case our customer was asking control to set POE mode from processor since they does not want 25.5W power at all the time 

    only one instance they will run their load at that power ratings, they doesnt want power wastage all the time.

    my idea to over come to switching circuit for CLS pin, i will use two resistor class 3  i.e 90.9 ohm and class 4 i.e 63.4ohm using optocoupler by giving control to select each CLS pin by processor.

    Please suggest more about CLS pin.

    I have attached  my plan in schematics ,please look at the once and tell me feasibility of that design .POE for TI review.pdf

  • Hi Namith,

    The class resistor should be chosen based on your expected max output power. For hardware classification, as soon as the PSE/PD is plugged together, the power chosen is locked and you can't change the resistance/system power unless you remove cable, change the resistor, and replug.

    The only way to change the power level actively while the PSE/PD is plugged in is through the data layer. This means a microcontroller on the PSE side and a microcontroller on the PD side communicating/negotiating through the data line what the power level should be.
  • Hi Darwin,

    I mean to say we will fix class resistor  first either  class 3 or class4. Then we provide  hardware control to select class by connecting hardware control  circuit  for class pin to vss.

    Ex:initially  will  fix our resistor to 63.4ohm then  it will run at class 4mode.

    Then based on our requirement  we will control another resistor by pulldown the intial class.

    Either way we will  fix our classification start up time only.

    I have sending  this through phone  please ignore typos. Difficult  to attach schematic for your reference.

    Regards,

    Namith

  • Hi Namith,

    Unfortunately, this approach will not work. When the PSE is initially plugged in and does detection then hardware classification to either Class 3 or 4, it will be locked at Class 3 or Class 4 after the PSE powers up to 48V. This means even if you change the class resistor after startup, it will not change the PSE system.

    To dynamically change the overall power of the system after plug-in, you must use the data lines (LLDP).

    Regards,

    Darwin

  • Hi Darwin,

    how are you,

    I have attached the schematic for POE mode selection feasibity, can check and confirm possibilty.

    Initial it is fixed to 90.9 ohm i.e MAX 12.5W 

    if we needed we can select other mode using GPIO

    Regards,

    Namith

    POE mode selection feasibility.pdf

  • Hi Namith,

    Is the GPIO signal available before plugging in PoE (microcontroller is powered by something other than PoE before plug in)? Then this solution could work. Be sure it's all referenced to VSS and not RTN.

    If GPIO signal is not available before plugging in PoE, then this solution may not work as described as my initial concerns in the previous post. Please let me know if this helps.

    Thanks!

    Regards,

    Darwin

  • Hello Darwin,

    I have a question regarding TVS diode used in reference schematic P/N:SMAJ58A  is 58V reverse voltage rated.

    Any reason for that.

    I understand that POE maximum voltage rating is 57V ,so selecting 58V rated is suitable, is it correct?

    Regards,

    Namith

  • Hi Namith,

    That's correct. In addition, the SMA is what we recommend in most indoor applications. If other electrical transients are expected (outdoor), then more protection will be needed.

    Regards,

    Darwin