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TPS23756: TSPS23756 CTL Pin understanding

Part Number: TPS23756

Hi Guys

As for the CTL Pin function, datasheet : CTL is the voltage-control loop input to the pulse-width modulator (PWM). Pulling VCTL below VZDC causes GATE to stop switching. Increasing VCTL above VZDC (0 duty cycle voltage) raises the switching MOSFET programmed peak current. The maximum (peak) current is requested at approximately VZDC + (2 × VCSMAX). The AC gain from CTL to the PWM comparator is 0.5. The internal divider from CTL to ARTN is approximately 100 kΩ.

So in my opinion, the CTL Pin is used to control the PWM pulse. It is related to the current limit. But I am confused how does this Pin work? and what is the meaning of Vzdc? or why is Vzdc? What is the condition when Vzdc is higher than Vctl or lower than Vctl? could you please explain how the CTL work ?

Any feedback are appreciated.

Thanks 

-Vincent

  • Hi Vincent,

    I am looking into your question & will give you a detailed response later this week.

    Thanks,
    Tom
  • Hello Vincent,

    I'm currently digging into your question and wanted to be sure I properly understand your post. I am preparing to answer the following questions:

    1. How does the CTL (control loop input) pin work?
    2. What is Vzdc (zero duty cycle threshold) & why is it important?
    3. What happens when Vctl > Vzdc? What happens when Vctl < Vzdc? 
    4. How is CTL & Vzdc related to the peak current limit?

    Please let me know if I am missing a portion of your post you also want answered.

    - Tom

  • Hello Vincent,

    #2. Vzdc (zero duty cycle threshold) is a 1.5V bandgap reference that the TPS23756's PWM controller uses to compare the CTL signal against. The PWM controller uses this constant bandgap in order to approximately know if the output voltage is within regulation.

    #1,3,4. When Vout is above you intended output voltage, the optocoupler in the feedback loop will conduct more, resulting in Vctl to decrease. If Vctl decreases below Vzdc, then the primary side FET turns off, ending the duty cycle because the secondary side does not need additional voltage to stay within regulation.

    When Vout is below your intended output voltage, the optocoupler conducts less. As a result, Vctl stays above Vzdc, so the PWM controller keeps the primary side FET on, lengthening the duty cycle. The longer the duty cycle, the higher the primary side peak current because the inductor of the primary side of the transformer becomes more like a short the longer a DC current is applied. The peak current can be reduced or increased based on how high or low the inductance of the transformer is, respectively.

    Thank you,
    Thomas Amlee
  • Thanks Thomas. Very nice explanation.