Hi TI,
We are planning on using the part CSD17313Q2Q1 in one of our upcoming designs.
Given below are the tentative design details:
Planned Scheme: Active OR-ing (i.e. tying the Drains of both N-FETs together and providing independent power supplies at the Source terminals)
Voltage at Source of 1st FET: 12V
Voltage at Source of 2nd FET: 5V
Load Current: 1A
Since we do not have separate Gate driving signal we are planning to connect the Source signal to Gate terminal.(effectively shorting Gate and Source terminals)
We have below mentioned queries:
1. Will this Active OR-ing circuit work ?
2. Ideally in this circuit Vgs would be zero hence N-FET will not turn ON, what are the changes we need to incorporate in the Gate driving side in order to turn ON N-FET?
3. Would the drop across the circuit be Current X Rds(on) or would there be any additional drop since the two FETs are connected ?
4. If this is not a suitable method please suggest the best alternate method for Active OR-ing two supplies using FETs.
A speedy response will be appreciated.
Regards,
Deepak Holla
Project Lead
L&T Technology Services
TC3, Tower A, 7th Floor
Manapakkam
Chennai-600 089.