This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CSD19533 - Thermal pad design

Other Parts Discussed in Thread: LM3152

Hi, 

I'm designing a 24V - 3.3V@2A DC/DC converter. I'm using LM3152 to control 2 CSD19533  in a synchronous buck topology. I'm using a 4 layer board. The thickness of the copper is 35 um (70um after plating) The "thermal pad" is connected to the drain of the device.  

How should I make the thermal pads? I'm thinking of making a a copper pour around 3 cm x 3 cm on bot(4) and top (1) layer and connect them with many vias. The component is located on top layer. Should I make extra clearance for the thermal vias on 3.3V (3) and GND layers(2) (maybe remove the copper in between the thermal pads all together). My main goals are minimise  ringing and noise and lower the operating temperature as much as possible.

Does the size of the thermal pads effect the ringing and noise of the converter? Eg if I made a large bottom pad (5x5 cm or larger).

I have look at some of the application notes but I mostly find how to place the components or how to make thermal pads for ICs that have the thermal pad connected to GND. If there is a example of how I should do this please link it.

Best regards,

Marko 

  • Marko, Let me run this by our packaging and layout guys and get back to you.
  • Got the following response:

    " They can drill thermal vias on the pad. Just follow the pad recommended footprint from the data sheet and drill thermal vias.
    As much as possible we need to plug the thermal vias to prevent solder flowing to the other side of the board.
    Don’t remove more Cu as it will create a big soldering voids and degrade your thermal performance."
  • Hi, 

    thank you for your response.

    I still have some questions. On the top fet I can connect the thermal vias directly to the Vin Cu pure. Vin will have decopling on it and its a stable (DC) plain. On the bottom fet the thermal vias are connected to the switching point - with high dv/dt. As I get it, I'm supposed to make a bottom Cu plain and then connect it with thermal vias right? Is there a size limit on the area of this plain (where the capacitance of the plains will increase ringing)?

    Best regards, 

    Marko 

  • "The contact area of that plain should not be lower than the contact area of the package to make sure there is no increase in capacitance. If [you] can share drawings the better."
  •  --Picture_1

     --Picture_2

     --Picture_3

    Hi, 

    This is a picture of my current PCB.

    Picture_1 - buck converter. A is marked +24V, that comes from the bottom layer. The device Q501 will get good heat sinking, it is connected to a big copper trace that is via stitched to the bottom layer. How do I cool Q502 that has its heat pad on SW (switch node)?

    Picture_2- boost converter. Again how do I cool Q601 that has its heat pad on SW node? 

    Picture_3-past mistake - making SW larger for heat sinking. The vias connect to a bottom layer copper pour as big as the ones on the top side. How do I get good heat sinking without making the same mistake again ?

    If I add vias under the pad of Q502 and Q601 do I connect the vias to a anything else on other layers (no right)? How many and how big do I make the heat vias? (smallest as I can ?)

    Best regards, 

    Marko 

  • Marko, Sorry for the delayed response.

    Here was the feedback from our applications team:

    "Unfortunately, the only way to heatsink the FETs that sit on Vsw is to increase the copper size add vias as he did on picture 3. Does he not like the layout for picture #3 because of noise or because it still got too hot? If it still got to hot, it may be due to the fact he has thermal relieves on the FET pads. He needs to remove these…"
  • The problem is that in picture 3 I had a lot of ringing as seen from this post and I don't want to make the same mistake again.  "increase the copper size add vias" Do I connect the vias to anything on bot layer or are the vias only connected to the copper on top plyer (e.g. do I increase the copper size by making it bigger on top layer or do I make a copper pour on bottom player and connect it via vias )?

    Best regards, 

    Marko 

  • Response from applications:

    Ringing and Thermals are two separate topics…

     

    For the Thermals: he should take the copper shape and size he has for Vsw on the top layer and replicate it on all the layers, including the inner and bottom layer.  He needs to remove all thermal relief connections to the FETs (see below).  In general, there should never be any thermal relief connections to any power node by any power component (this includes FETs, Caps, Inductors, etc.).

     

    For the Ringing: he needs to install the snubber network in his schematic (R106-C103 and R107-C104).  He needs to tune the snubber based on the attached App Note.


    slup100.pdf