We are currently applying MOSFET IPZ65R019C7 in Kelvin source configuration and TI gate driver UCC27714DR. The FETs are driven with 250kHz and pulse width of 400us. The schematics is as follow:
The driving signal for the FET drivers are shown as follow:
The following is the scope shot for the gate to source voltages of M2 and M4 on the schematics
(Yellow being gate to source of FET M2, blue being gate to source of FET M1)
(voltage pulse that occurs on the low-side FET’s gate when the high-side FET of the A side of the bridge turns on for the first time)
From simulation and scope shot, we are able to see the voltage spike on the first pulse ( or when current starts to flow) which would potentially exceed maximum gate to source breakdown voltage and damage the FET. The spike voltages shown on subsequent pulses are not as dramatic as the first voltage spike. We found out that voltage spike is potentially caused by node inductance (L1, L12, L5, L7 on the schematics).
Any suggestions on how to get rid of the first pulse?
Thanks,
Jay