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UCC27714DR High Voltage H bridge Gate Driver

We are currently applying MOSFET IPZ65R019C7 in Kelvin source configuration and TI gate driver UCC27714DR. The FETs are driven with 250kHz and pulse width of 400us. The schematics is as follow:

 The driving signal for the FET drivers are shown as follow:

 The following is the scope shot for the gate to source voltages of M2 and M4 on the schematics

  (Yellow being gate to source of FET M2, blue being gate to source of FET M1)

(voltage pulse that occurs on the low-side FET’s gate when the high-side FET of the A side of the bridge turns on for the first time)

 From simulation and scope shot, we are able to see the voltage spike on the first pulse ( or when current starts to flow) which would potentially exceed maximum gate to source breakdown voltage and damage the FET. The spike voltages shown on subsequent pulses are not as dramatic as the first voltage spike. We found out that voltage spike is potentially caused by node inductance (L1, L12, L5, L7 on the schematics). 

 Any suggestions on how to get rid of the first pulse?

Thanks,

Jay

  • Jay, let me discuss this with my applications team and get back to you.
  • Brett, 

    Thanks. I took more pictures today and hopefully it helps you to understand the problems.

    Yellow and Blue waveforms are gate to source voltages of lower two FETs and Green waveform is voltage across two switch nodes.

    Thanks again for the help,

    Jay

  • Jay, Applications first wanted to verify that the spike you are seeing is real.

    Can you confirm? Are you using a higher frequency, small differential probe w/ a small low ground loop?
  • Brett,

    We are sure that spike is real. We have used high frequency diff probe and connected them right on the gate and source pin of the FET with a really small ground loop. The waveform always looks exactly the same as the simulation. So with simulation to back it up, we think the spike is real.

    Thanks,
    Jay
  • The waveform looks almost exactly the same as the simulation.
  • Jay,
    A few questions. First, why are there inductors (L1, L5, L12, L7) in the return path of the gate drive loop? Also, why is the gate spike not seen on subsequent switching events - only when the low side is completely off? This seems to be a C dv/dt induced gate spike, which may be exacerbated by these inductors (L1, L5,L12, L7).
  • Brett,

    L1, L5, L12, L7 are the PCB parasitic inductance. We already minimized the return loop as much as we could but we are still seeing the first spike.

    The low side gate not really that close to the high side source, but we do believe that the problem is partially due to the Miller effect. During idle state the two low-side FETs are on to ensure that both boot caps are charged. Before the first switch pulse all FETs are turned off to get the bridge ready to start switching. When the FETs are off and there is 0 volts across them, the Ciss, Coss, and Crss capacitances are greater than 10nF (per the datasheet). As M1 turns on, current starts to flow through that FET and charges the capacitances on the low-side FET. Because of the capacitive divider between the Miller capacitance and the gate-to-source capacitance, the voltage between the gate and source sense does rise somewhat. You can see that occurring in scope shot TEK00064. But the scope shot also shows that this voltage should be at or below the turn-on threshold of the FET, at least at a level that doesn’t appear to support large amounts of current flowing through the channel of the FET. Rather, we believe that the current that flows through the FET is a result of the Coss charging that takes place as current flows through the high-side FET. This current also flows through the low-side FET’s source inductance. After the Coss capacitance is charged and current stops flowing, the polarity of the source inductance flips and the voltage at the source goes negative. Simulation tends to support this theory in that by essentially shorting the gate of the low-side FET to its source sense (ensuring that the FET is held “off”), current still flows into the drain of the low-side FET.