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CSD19536KTT: CSD19536KTT / Oscillation used with LM5060

Part Number: CSD19536KTT
Other Parts Discussed in Thread: CSD19536, TINA-TI, BQ76200, LM5060, BQ76930

Hi,

Now my customer is evaluating LM5060EVM and they replace external FET from SUM40N10-30-E3 (default) to CSD19536KTT. Then they confirmed current oscillation as attached. After that, they added 100ohm gate resistor then the oscillation is prevented. So please let me ask following question.

  1. Can you give your comment why such oscillation is happened?
  2. Can you give your comment why this oscillation is prevented by adding gate resistor?

Please let me know if you need more information. Please also refer this thread that is posted to hot swap forum.

Best Regards,

Satoshi / Japan disty

  • Satoshi-san,
    I've reached out to our apps team for some clarification. I hope to have a response to you shortly.
  • Hi Brett,

    I appreciate for your support. I'm waiting for your update.

    Best Regards,
    Satoshi
  • Hi Brett,

    Do you have any update? Your kind response will be appreciated.

    Best Regards,
    Satoshi
  • Sorry for the delay,
    Reply came in over the weekend:

    "It depends on how the driver circuit is. CSD19536 has very low gate charge so fast gate driver may cause oscillations. Adding 100Ohm Rg slows the gate driver down hence eliminates the oscillation."

    Basically, they just think because the CSD19536 is a relatively fast switching FET, that was probably why you were seeing some ringing.
  • Hi Brett,

    Thank you for your comment. As you commented, I also think that it needs to add Rg when the FET has low gate charge, then do you have any way to calculate (estimate) Rg for used FET? Or can I see such oscillation by using TINA-TI Spice Model? I understand that it should be deiced with cut & try, but I'd like to estimate Rg before evaluation.

    I checked that CSD19536 is used with bq76200, bq76930 and also LM5060 in TI Designs.

    Best Regards,
    Satoshi
  • Satoshi,
    I don't think there is an app note on this, but I have reached out to the apps folks to see if they have any advice.
  • Hi Brett,

    Thank you for your support. The customer understood the necessity of gate resistor and consider to add it. But then he needs to explain internally the reason why such oscillation is induced and it can be fixed by adding gate resistor. So it will be appreciate if you ask it your app team.

    Best Regards,

    Satoshi

  • Satoshi,
    Here is a bit more thorough response:

    "The oscillation present on FETs Gate terminal bounces around FET Vth threshold and causes parasitic successive turn ON/ turn OFF events. As a result, drain current and Voltage oscillations are being generated. Through FETs Miller Cgd capacitance effect, feedback path drain-to-gate is always present.

    Mainly, the oscillations appear due to parasitic pcb trace inductances for Gate, drain and source connections. Together with the MOSFET Ciss and Coss capacitance parameters , LC tanks are energized.
    The external gate Rg is used to dampen the gate Oscillations by lowering the Q( Quality factor) of the gate RLC equivalent circuit.

    For a numerical simulator like TINA-TI or Pspice to replicate oscillations like seen in real world, the PCB parasitic model comprised of accurate L+C values must be well known.
    Without the circuit parasitics properly included in the simulator , the simulations show ideal results and clean waveforms.

    Keep in mind LM5060 is Hot swap, linear application. The FET gate is being driven with 16uA current with a current mirror.
    There’s No “recipe” to calculate/predict the System oscillation, or rather to say: use xxx value and Oscillation is gone.
    Moreover, simply trying in Tina the LM controller + FET model and no oscillation / intermittent start-up can be duplicated."