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TIDA-00364: What are 12v power supply requirements for this design? Max current? Regulated?

Vlad Blanshey
Intellectual 690 points
Part Number: TIDA-00364
Other Parts Discussed in Thread: UCC27212, UCC27211, TIDM-1003, , CSD19536KTT

Hello, to be specific - what are the requirements for external power supply 12v to drive parallel MOSFETS in this design? Max current? Regulated?

In general I'd like to understand how to figure 12v current requirements to drive TI UCC27211/UCC27212 gate drivers used in a number of reference designs.

Another one is TIDM-1003 using the same TI pre-driver chip.   12v supply is external but no mentioning on the current requirements.

Thanks in advance for any help

  • 0
    TI__Mastermind 20950 points
    Hello,
    I am an applications engineer at TI and will work to help answer your questions. I can give advice on how to determine the bias current required for the gate driver and gate drive power for specific MOSFETs.
    For more detailed information on the TIDM-1003 and TIDA-00364 please start a new inquiry on these specific designs to communicate with engineers more familiar with these designs.
    For the gate driver requirements, refer to the UCC27212 datasheet section 8.2 for the typical application design. The gate driver current requirements will be comprised of Iq, quiescent current of the driver, and the average current required to drive the MOSFET(s) charge. The design information indicates calculating the Pg, or gate drive power; for the current just remove the VDD term to determine the average current. The total gate charge of the MOSFET(s), Qg, is usually specified in the datasheets.

    Regards,
    Richard Herring
  • 0 in reply to Richard Herring
    Intellectual 690 points
    Thank you for reply,
    Trying to apply Sec. 8.2 using TI NexFET csd19536ktt - total switching gate charge Qg = 153 nC max or 0.000000153 C and switching frequency used in this TIDA is 10 kHz:
    Pdiss ~ only switching is significant Psw = Qg x Vdd x Fsw = Ig x Vdd so current Ig = Qg x Fsw = (coulomb) x (Hz) = Amps
    So charging average current at max gate charge Ig = Qg x Fsw = 0.000000153C x 10000Hz = 0.00153A
    This cannot be right... What is it for the 4 A sink and 4 A source output current if not for charge/discharge of the gate capacitance? Please point to error here
  • 0 in reply to Vlad Blanshey
    Intellectual 690 points
    Also this MOSFET gate charging is not the only consumer of supply power Vdd but the bootstrap capacitor also gets charged from Vdd through the gate driver chip, so the section you pointed is only part of the Vdd power usage in a gate driver chip...
    Please correct me if I am wrong
  • 0 in reply to Vlad Blanshey
    TI__Mastermind 20950 points
    Hello Vlad,
    For the power consumption for driving the MOSFET gate, or total gate drive power dissipation, the power dissipated is related to the voltage charged and discharged on each cycle and the effective capacitance of the gate driver load.
    The rate at which the Mosfet gate is charged and discharged actually does not change the power related to the charge and discharge of the effective capacitance. The 4A peak gate driver currents will be extremely low duty cycle in a 10kHz application which will result in relatively low average current.
    For the additional message of the VDD current is also charging the bootstrap capacitor. The power transferred to the bootstrap capacitor will be supplying the HB Iq current plus the gate drive energy for the high side gate drive.
    After review, I see that the UCC27212 section 8.2 is not specific that the gate charge Qg does indeed need to include the gate charge of the high side MOSFETs and the low side MOSFETs. Total gate charge of the MOSFET load of the driver.
    Also the quiescent current will be IDD + IHB.
    In your case: if the LO and HO are both driving 153nC gate charge, at fsw of 10kHz. The gate drive related current is 2 x 153nC x 10kHz= 3.06mA. The Idd and IHB is 140uA + 1uA (maximum). The total is ~3.071mA.
  • 0 in reply to Richard Herring
    Intellectual 690 points
    Thank you Richard, I started getting closer to understanding how bouncing of the same total amount of charge occurs between Vdd, HO, LO, HB and the MOSFET gates. I missed that the specified rate of sink and source currents means only peak for a low duty cycle, not average, neither RMS.
    So the driver which drives very powerful inverter stage (130Amps continuous output to the motor coils) uses ONLY 3mA from 12v source per block of inverters, total from 12v -> 9mA for all 3 phases !
    Please confirm that now I got it right :)
    Thanks again
    BTW: this TI inverter ref design is unique - there are no other examples on internet of high power motor drives starting from pre-drivers ending with parallel MOSFETS for high current. I am glad TI did it.