Hello.
I'm not sure what the "Gate Clump Current" refers to.
I'm designing a board where real-estate is very limited. I'd like to use CSD75208W1015 as a high-side FET.
The rail is about 8V which is higher than the maximum Vgs (-6V). I'd like to pull down the gate to Ground through a resistor but not to use a zener or resistor voltage divider to save space.
Assuming I use a, e.g. 1K, resistor for pull down, would the gate clamp limit diode the voltage to acceptable levels? since 8[mA] is much less than the allowed -0.5[A].
Is that what the term means? I saw no charts detailing the Vgs vs. current and I'd hate to find out the hard way.