LMZ10503: LMZ10503: Failures at lighter load

Part Number: LMZ10503

Dear Sirs,

in our radar sensor, we are currently experiencing some failures of your integrated DCDC converter, the LMZ10503.

The fact. Each radar has two digital boards; each of them mounts a LMZ10503 to produce a 3.3V rail for the internal peripherals.

The board #1 has a load of 340mA, and the board #2 has a load of 130mA; the boards are identical (I mean they have the same BOM), but the brd#1 provides also the 3.3V for an external module, so this explains the extra load current.

We have produced 384 pieces of digital boards, 192 mounted as brd #1, 192 mounted as brd#2 and we have experienced 15 failures only on the brd #2, due to the damage of LMZ10503.

The LMZ10503 mounted on board #2 (the one with 130mA) works in FCCM (Forced Continous Conduction Mode).

Although the synchronous buck converter allows the FCCM, my  idea is the LMZ10503 with a lighter load is more stressed, perhaps due to the inductor current flowing in both directions (assuming as forward the direction of load current): to reinforce the correctness of this hypothesis, the LMZ mounted on board #1 has never failed yet.

Operating conditions. The LMZ10503 derives the 3.3V from a 5V input dc voltage (supplied from an external AC/DC converter); so the buck ripple current, with a duty cycle of 0.66, L=2.2µH, and fsw=1MHz, is:

From the equation above, the board #2 is surely functioning in FCCM, while the board #1 is weakly or not in FCCM.

Simulation. To demontrate the FCCM mode, I also performed a PSPICE simulation using the TI LMZ Pspice model; see the schematics and plot below:

Boards workaround. To limit the reworking intervention on hundreds of boards, I suggested -as praticable workaround- the introduction of  a 15Ω resistor (a dummy load) on 3.3V rail, to port the overall load to 342mA, so equalizing the load on each board. Further, on brd#2, I have also increased the output capacitor value to 100µF to improve the filtering.

In the simulation, I implemented the workaround and I introduced a variable load to test the loop stability: see below:

Testing the workaround. As further step, to test the solution described, we applied the workaround on a batch of 10 radar, leaving them powered without interruption; after more of one month of continuous working the results was no LMZ has failed.

Here my questions for you:

  1. Could be the FCCM a reasonable explanation for the LMZ failures?
  2. Do you have any other explanation?

Thank you very much for any help

Marco Fogli











  • Hello Marco,

    Thank your detailed post.

    I don't see a good reason why the part could fail in light load vs slightly higher load. It is a bit difficult to read the component values in the schematic (I think it is image resolution issue). It looks like you had 4.7uF output capacitor, but it could be 47uF. It is hard to tell from the image. Please confirm.

    You mention that you added 100uF.

    Simulation suggests that with
    4.7uF output capacitor,
    270pF and 105ohm compensation values,
    18k and 5.76k feedback resistors
    the design is very unstable.

    with 47uF output capacitor,
    270pF and 105ohm compensation values,
    18k and 5.76k feedback resistors
    you would get about 160kHz xover and 30degrees of phase margin

    with 4.7uF + 100uF
    270pF and 105ohm compensation values,
    18k and 5.76k feedback resistors
    you would get about 75kHz xover and 43degrees of phase margin

    with 47uF + 100uF
    270pF and 105ohm compensation values,
    18k and 5.76k feedback resistors
    you would get about 60kHz xover and 40degrees of phase margin

    This is all assuming the capacitors on the output do not de-rate under the voltage bias.

    1. Did you update any of the compensation components when you added more capacitance?
    2. Can you confirm if the output cap is ceramic and what is the voltage rating and case size of the part?
    3. Could you share the board layout (at least the portion with the LMZ regulator) for review?
    4. Can you please describe the failure mode of the regulator? For example, is the output voltage still present, but incorrect value, or is it 0V?

  • In reply to Denislav Petkov:

    Hi Denislav,

    Thank you very much for the prompt response; in general sound strange to look at light load as cause of failure, but consider that the LMZ on board #1, never fail.

    From your answer, seems you suspect the instability condition as reason of failure: it is so? Consider the board has also about 8 µF of disseminate ceramic capacitors, on 3.3V rail. In every case, I agree to increment the output capacitor, as was done in the trial of 10 radar.

    Regarding the stability, do you consider enough to increment the output capacitor to 100 µF, with 75kHz crossover frequency and 43° of phase margin? From my simulation, with pulsed load, the system seems stable.

    Here the answers to your questions:

    1. No, I don’t update the compensation components with the 100µF;
    2. Yes, the output capacitor is ceramic, 4.7 µF, 16V X7R, 1206: CGJ5L2X7R1C475K160AA (Digikey pn 445-8225-2-ND);
    3. Yes but I should ask to my colleagues for the brd or gerber file: I hope to send you as soon as possible;
    4. Hearing from my colleagues, when the LMZ fail, seems its output voltage drops to 0.8V; but I do not know if this behavior is recurring or not.

    Best regard


  • In reply to Marco Fogli:

    Hello Marco,

    Thank you for the details.

    Here are a few more comments. 

    1.The input capacitor value (only 1uF) and placement can definitely be improved. The input capacitor and the internal power MOSFETs form a high di/dt loop. The area of this loop is proportional to the loop inductance. The higher the loop inductance (together with the high di/dt) will result in higher noise. I would suggest placing the input capacitor on the same layer as the LMZ device and right next to the VIN and large GND pad.

    Also, I would strongly suggest increasing the input capacitor to 22uF. See page 15 of the DS for suggestions.

    2. Increasing the output capacitance to 100uF should help. Please ensure that this ceramic capacitor is sufficiently rated (perhaps 10V cap 1210 case size) so that it does not de-rate its capacitance value under the 3.3V DC bias.

    You can also use WEBENCH to improve the component values. 

    Here is what the tool suggests for your design parameters (5V input, 3.3V output):

    And here is the frequency response simulation:



  • In reply to Denislav Petkov:

    Hi Denislav,

    thank you again.

    I agree your suggestions.

    Input capacitor.

    Increasing the input capacitor and putting it closer to input pin. I think the lack of capacitor near the input pin is, probably, the cause of the LMZ damage, due, perhaps, to a voltage spike, related to di/dt and higher loop inductance.


    As you have indicate before, I have performed an AC simulation using Webench; after I repeated the simulation with Pspice on my PC, using the TI LMZ model. The result suggests is convenient to change the feedback and compensation network, with the values you proposed, to obtain more phase margin.

    Best regards

    Marco Fogli