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Part Number: LMZ31710
Hello I am designing in an LMZ31710 for my next PCB design. I am reviewing the recommended layout and I notice in figure 45 of the datasheet there is a cap marked cin4. I do not see any reference to cin4. Can you clarify this capacitor and its value please.
From the layout, the Cin4 should be a high frequency bypass cap between VIN and ground, for pin 11/12 and pin 20/21, on this side of the module. It should be a low capacitance ceramic cap, around 1 uF should be fine. The voltage rating should be >150% of VIN.
TI Wide Vin Buck Converter & Controller Applications Engineer
In reply to YangZhang:
BSR-CCP LV/MV DC/DC Applications
In reply to JohnTucker:
Hi John and Yang. Thank you for your replies.
I am still a bit confused. As you can see in the layout in figure 45 there are four capacitors not three, CIN1 through CIN4. There is no mention of CIN4 in the datasheet other than in figure 45.
So just to be clear as I have understood it from both of your repsonese and please see copied attached reference layout for these comments
CIN1 = 100uF input capacitor
CIN2 = 47uf ceramic pvin pins 1,39,40
CIN 3 = 0.1 uF ceramic pvin pins 11 and 12
CIN4 = 1.0 uF ceramic pvin 11,12 and GND pin 20/21
In reply to guy lemire:
Hi John and Yang, thank you for your input. I have another question regarding the layout. In the data sheet it shows an island for the PH pins on all inner layers. How critical is this to have these pins this isolated? I have a 12 layer PCB, should this island be propagated through all the layers?
I believe the island of PH was propagated to all the layers for thermal dissipation purposes. It will help with getting some heat out of the device. The trade-off of propagating the PH node to other layers is potential noise coupling. I would suggest forcing more clearance between the PH island and nearby copper. This would minimize any capacitive coupling to the nearby nodes. The top and bottom layers will be the most effective for getting the heat out to the ambient. Perhaps you can use copper islands on the outer layers so that you still get the thermal benefit and minimize potential noise coupling.
I will also contact the Apps engineer who worked on this board. He may have some more suggestions.
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