• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 62 subscribers
  • Views 532 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Inquiry regarding input capacitor of DCP010512DB

Atsushi Okui
Genius 4015 points
Other Parts Discussed in Thread: DCP010512DB

Hello, all

Now we have some inquiries regarding input capacitor of DCP010512DB.

Please refer to the items below, and feedback us with your comment.

1) When referring page 2 of SBVA013A, the ESR requirement for input capacitor is important for stability on starting up.

However, if we could chose good ESR capacitor (less than 20mohm), the capacitance itself is higher than 2.2uF, which is specified on the datasheet (3.4uF).

Please let us confirm whether this 3.4uF input capacitance could some influence on the operation of this device.

2) When referring page 13 of SBVS012E, in case that input voltage is fallen below approximately 4V, the DCP will detect an under voltage condition.

However, when testing this sample, DCP010512DB seems to detect under voltage condition in case falled below 3.3V. In case 3.3 to 4V input, DCP010512DB tried to output, but this was result in failed.

Please let us know what is the correct operation in case of under voltage condition on this device.

We thank you in advance for your information.

Best regards, 

  • 0
    TI__Mastermind 38230 points

    If the input decoupling capacitor is not ceramic with < 20mΩ, ESR, then at the instant the power transistors switch on, the input voltage will fall below 3.6-4V. The DCP series will detect an UVLO   voltage condition and switch the DCP drive circuits to the off state. This UVLO design is necessary to protect the internal circuit from driving the transistors into saturation. If the transformer saturation were to continue, it is possible to overstress the converter.

     The UVLO (< 4.0V)   protects the converter during the UVLO detect by cycling the converter. This detected cycling forces the input voltage / power bus converter to increase its in-rush current.

    If the power source is cannot source sufficient current (up to 750mA), the converter will oscillate loading down the power source or with bus resistance voltage cycles below UVLO will occur.

    There are several methods, which can be implemented to minimize input in-rush current.

    a. Grounding the sync. input pin (also on-off pin), pin 14, for 3-5ms, after Vin is 5V, delays the switching cycles, and it allows the input ceramics capacitors to be an additional current and impedance matching source.

     I attached a application schematic for delayed control of the pin 14 input sync. pin.

    Tom

    DCP0105xxx SVS UVLO single_dual .pdf
  • 0 in reply to Tom Guerin
    Genius 4015 points

    Hello, thank you for your prompt reply.

    On their system configuration, Sync pin(14) is unused, and there is not enough place to have modification. This means that only way to keep low ESR on input, the Cin capacitance itself need to be increased from 2.2uF.

    Therefore, please let us clarify how the operation of DCP010512DB could be affected if input capacitance is increased from 2.2uF to3.4uF.

    We thank you in advance for your information.

    Best regards,

  • 0 in reply to Atsushi Okui
    TI__Mastermind 38230 points

    Atsushi Okui:

    The input ceramic capacitor increase to 3.4uF or 10 uf will not affect the inrush current sinked  by the DCP010512DBP from the output of the 5V power source  regulator.

    One suggestion is to increase or change the input  5V power regulator to a higher current device.The input 5V  power source is being driven into over current protection(OCP).

    Tom

     

  • 0 in reply to Tom Guerin
    Genius 4015 points

    Hello, thank you for your reply. 

    Now we have additional inquiry regarding this device's behavior in case of undervoltage condition. 

    When referring page 13 "Input Capacitor and the effects of ESR" of this datasheet, there is a description  as below;

    This is carried out as a precaution against a genuine low input voltage condition that could slow down or even stop the internal circuits from operating correctly. 

    Please let us clarify whether you have particular threshold level to switch the internal circuits to either slow down or stop.

    We thank you once again for your information.

    Best regards,

  • 0 in reply to Atsushi Okui
    TI__Mastermind 38230 points

    The DCP series will detect an UVLO   voltage condition and switch the DCP drive circuits to the off state. This UVLO design is necessary to protect the internal circuit from driving the transistors into saturation.

    The UVLO (typically< 4.0V)   protects the converter during the UVLO detect by cycling the converter. This detected cycling forces the input voltage / power bus converter to increase its in-rush current.

    If the power source is cannot source sufficient current (up to 750mA), the converter will oscillate loading down the power source or with bus resistance voltage cycles below UVLO will occur.

    . One method which can be implemented to minimize input in-rush current is delay the switching function .

    By grounding the synchronization input pin (also called on-off pin) for 3-5ms, after Vin is applied , delays the switching cycles, which  allows the external input ceramics capacitors to be an impedance matching source.

    I attached a application schematic for delayed control of the input synchronization  pin,

    Tom

     

    DCP0x05xx SVS UVLO single_dual .pdf
  • 0 in reply to Tom Guerin
    Genius 4015 points

    Hello, thankl you for your prompt reply.

    As you mentioned above, when the input voltage will fall below 3.6 - 4V, the DCP series will detect an UVLO.

    However, on their board, ULVO was detected on 3.4 - 4.1V when the temperature range was varied from 0 to 50 degree.

    I assume that 3.6 - 4V UVLO detection range was when the temperature was 25 degree.

    Please let us clarify whether the UVLO detection range itself could be either higher or lower than 3.4 - 4.1V.

    We thank you once again for your information.

    Best regards,

  • 0 in reply to Atsushi Okui
    TI__Mastermind 38230 points

    Hello:

    UVLO  at 3.6V is a typicial voltage .There is no specific UVLO by design. The UVLO can be as low as 3V depending upon the measurement technique and the  power source(5V) current limit.

    Tom  

  • 0 in reply to Tom Guerin
    Genius 4015 points

    Hello, thank you for your prompt reply.

    Please let us clarify how UVLO could be high depending upon the measurement technique and etc as well. (when using ceramic with < 20mΩ ESR)

    We thank you once again for your information.

    Best regards,

  • 0 in reply to Atsushi Okui
    TI__Mastermind 38230 points

    Hi :

    TheUVLO range on the DCx isolated converters is an approximate number. It is not defined to  a specific point or range. The estimate range is between 3.2V to 3.8V.
    Tom